| A 28-GHz CMOS phased-array transceiver based on LO phase-shifting architecture with gain invariant phase tuning for 5G new radio J Pang, R Wu, Y Wang, M Dome, H Kato, H Huang, AT Narayanan, H Liu, ... IEEE Journal of Solid-State Circuits 54 (5), 1228-1242, 2019 | 205 | 2019 |
| A 28-GHz CMOS phased-array beamformer utilizing neutralized bi-directional technique supporting dual-polarized MIMO for 5G NR J Pang, Z Li, R Kubozoe, X Luo, R Wu, Y Wang, D You, AA Fadila, ... IEEE Journal of Solid-State Circuits 55 (9), 2371-2386, 2020 | 195 | 2020 |
| A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB AT Narayanan, M Katsuragi, K Kimura, S Kondo, KK Tokgoz, K Nakata, ... IEEE Journal of Solid-State Circuits 51 (7), 1630-1640, 2016 | 146 | 2016 |
| A 50.1-Gb/s 60-GHz CMOS transceiver for IEEE 802.11 ay with calibration of LO feedthrough and I/Q imbalance J Pang, S Maki, S Kawai, N Nagashima, Y Seo, M Dome, H Kato, ... IEEE Journal of Solid-State Circuits 54 (5), 1375-1390, 2019 | 89 | 2019 |
| 14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique W Deng, D Yang, AT Narayanan, K Nakata, T Siriburanon, K Okada, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 65 | 2015 |
| ULPAC: A miniaturized ultralow-power atomic clock H Zhang, H Herdian, AT Narayanan, A Shirane, M Suzuki, K Harasaka, ... IEEE Journal of Solid-State Circuits 54 (11), 3135-3148, 2019 | 55 | 2019 |
| A 60-GHz 3.0-Gb/s spectrum efficient BPOOK transceiver for low-power short-range wireless in 65-nm CMOS Y Wang, B Liu, R Wu, H Liu, AT Narayanan, J Pang, N Li, T Yoshioka, ... IEEE Journal of Solid-State Circuits 54 (5), 1363-1374, 2019 | 45 | 2019 |
| A 28GHz CMOS phased-array transceiver featuring gain invariance based on LO phase shifting architecture with 0.1-degree beam-steering resolution for 5G new radio J Pang, R Wu, Y Wang, M Dome, H Kato, H Huang, AT Narayanan, H Liu, ... 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 56-59, 2018 | 45 | 2018 |
| 24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802. 11ay with calibration of LO feedthrough and I/Q imbalance J Pang, S Maki, S Kawai, N Nagashima, Y Seo, M Dome, H Kato, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 424-425, 2017 | 45 | 2017 |
| A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration B Liu, Y Zhang, J Qiu, HC Ngo, W Deng, K Nakata, T Yoshioka, J Emmei, ... IEEE Transactions on Circuits and Systems I: Regular Papers 68 (2), 603-616, 2020 | 42 | 2020 |
| High- Inductors on Locally Semi-Insulated Si Substrate by Helium-3 Bombardment for RF CMOS Integrated Circuits N Li, K Okada, T Inoue, T Hirano, Q Bu, AT Narayanan, T Siriburanon, ... IEEE Transactions on Electron Devices 62 (4), 1269-1275, 2015 | 34 | 2015 |
| 0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur H Zhang, AT Narayanan, H Herdian, B Liu, Y Wang, A Shirane, K Okada 2019 Symposium on VLSI Circuits, C38-C39, 2019 | 26 | 2019 |
| A 1.2 ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique B Liu, HC Ngo, K Nakata, W Deng, Y Zhang, J Qiu, T Yoshioka, J Emmei, ... 2018 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2018 | 25 | 2018 |
| A pulse-tail-feedback VCO achieving FoM of 195dBc/Hz with flicker noise corner of 700Hz AT Narayanan, N Li, K Okada, A Matsuzawa 2017 Symposium on VLSI Circuits, C124-C125, 2017 | 19 | 2017 |
| A 0.4-ps-jitter− 52-dBc-spur synthesizable injection-locked PLL with self-clocked nonoverlap update and slope-balanced subsampling BBPD B Liu, HC Ngo, K Nakata, W Deng, Y Zhang, J Qiu, T Yoshioka, J Emmei, ... IEEE Solid-State Circuits Letters 2 (1), 5-8, 2019 | 16 | 2019 |
| A pulse-driven LC-VCO with a figure-of-merit of− 192dBc/Hz AT Narayanan, K Kimura, W Deng, K Okada, A Matsuzawa ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), 343-346, 2014 | 14 | 2014 |
| 29.4 Ultra-Low-Power Atomic Clock for Satellite Constellation with 2.2×10-12 Long-Term Allan Deviation Using Cesium Coherent Population Trapping H Zhang, H Herdian, AT Narayanan, A Shirane, M Suzuki, K Harasaka, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 462-464, 2019 | 12 | 2019 |
| A 100mW 3.0 Gb/s spectrum efficient 60 GHz Bi-Phase OOK CMOS transceiver Y Wang, B Liu, H Liu, AT Narayanan, J Pang, N Li, T Yoshioka, ... 2017 Symposium on VLSI Circuits, C298-C299, 2017 | 8 | 2017 |
| A 0.048 mm 2 3 mW synthesizable fractional-N PLL with a soft injectionlocking technique W Deng, D Yang, AT Narayanan, K Nakata, T Siriburanon, K Okada, ... ISSCC Digest of Technical Papers 1, 2015 | 8 | 2015 |
| A pulse VCO with tail filter H Zhang, AT Narayanan, B Liu, K Okada, A Matsuzawa 2017 IEEE Asia Pacific Microwave Conference (APMC), 942-945, 2017 | 6 | 2017 |
