| RapidSmith: do-it-yourself CAD tools for Xilinx FPGAs C Lavin, M Padilla, J Lamprecht, P Lundrigan, B Nelson, B Hutchings Field Programmable Logic and Applications (FPL), 2011 International …, 2011 | 183 | 2011 |
| RapidWright: Enabling custom crafted implementations for FPGAs C Lavin, A Kaviani 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom …, 2018 | 138 | 2018 |
| HMFlow: Accelerating FPGA compilation with hard macros for rapid prototyping C Lavin, M Padilla, J Lamprecht, P Lundrigan, B Nelson, B Hutchings Field-Programmable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual …, 2011 | 128 | 2011 |
| Rapid prototyping tools for FPGA designs: RapidSmith C Lavin, M Padilla, P Lundrigan, B Nelson, B Hutchings Field-Programmable Technology (FPT), 2010 International Conference on, 353-356, 2010 | 70 | 2010 |
| RapidStream: Parallel Physical Implementation of FPGA HLS Designs L Guo, P Maidee, Y Zhou, C Lavin, J Wang, Y Chi, W Qiao, A Kaviani, ... | 46 | 2022 |
| Using hard macros to reduce FPGA compilation time C Lavin, M Padilla, S Ghosh, B Nelson, B Hutchings, M Wirthlin Field Programmable Logic and Applications (FPL), 2010 International …, 2010 | 36 | 2010 |
| RWRoute: An Open-source Timing-driven Router for Commercial FPGAs Y Zhou, P Maidee, C Lavin, A Kaviani, D Stroobandt ACM Transactions on Reconfigurable Technology and Systems (TRETS) 15 (1), 1-27, 2021 | 26 | 2021 |
| Space-Time Coding for Aeronautical Telemetry: Part I—Estimators M Rice, J Palmer, C Lavin, T Nelson IEEE Transactions on Aerospace and Electronic Systems, 2017 | 23 | 2017 |
| Impact of hard macro size on FPGA clock rate and place/route time C Lavin, B Nelson, B Hutchings Field Programmable Logic and Applications (FPL), 2013 23rd International …, 2013 | 23 | 2013 |
| Space-Time Coding for Aeronautical Telemetry: Part II—Decoder and System Performance M Rice, T Nelson, J Palmer, C Lavin, K Temple IEEE Transactions on Aerospace and Electronic Systems, 2017 | 22 | 2017 |
| RapidSmith–A Library for Low-level Manipulation of Partially Placed-and-Routed FPGA Designs C Lavin, M Padilla, J Lamprecht, P Lundrigan, B Nelson, B Hutchings, ... Technical Report, Dept. of Elec. and Comp. Eng., Brigham Young University, 2012 | 21 | 2012 |
| An Open-source Lightweight Timing Model for RapidWright P Maidee, C Neely, A Kaviani, C Lavin | 13 | 2019 |
| Improving clock-rate of hard-macro designs C Lavin, B Nelson, B Hutchings Field-Programmable Technology (FPT), 2013 International Conference on, 246-253, 2013 | 10 | 2013 |
| Using hard macros to accelerate fpga compilation for xilinx fpgas CM Lavin Brigham Young University-Provo, 2012 | 9 | 2012 |
| Build Your Own Domain-specific Solutions with RapidWright: Invited Tutorial C Lavin, A Kaviani Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019 | 8 | 2019 |
| Software-like compilation for data center FPGA accelerators J Thomas, C Lavin, A Kaviani Proceedings of the 11th International Symposium on Highly Efficient …, 2021 | 6 | 2021 |
| An FPGA-based space-time coded telemetry receiver C Lavin, B Nelson, J Palmer, M Rice Aerospace and Electronics Conference, 2008. NAECON 2008. IEEE National, 250-256, 2008 | 6 | 2008 |
| A library for low-level manipulation of partially placed-and-routed FPGA designs C Lavin, M Padilla, J Lamprecht, P Lundrigan, B Nelson, B Hutchings, ... Technical report, Brigham Young University, 2010 | 4 | 2010 |
| Rapidwright documentation C Lavin, A Kaviani | | 2020 |
| Reliability Models for Memory and FPGAs using Scrubbing JP Anderson, D Frei, D Gibelyou, B Heiner, J Heiner, J Johnson, C Lavin, ... | | 2008 |
