| The EPFL logic synthesis libraries M Soeken, H Riener, W Haaswijk, E Testa, B Schmitt, G Meuli, F Mozafari, ... arXiv preprint arXiv:1805.05121, 2022 | 133 | 2022 |
| A Versatile Mapping Approach for Technology Mapping and Graph Optimization AT Calvino, H Riener, S Rai, A Kumar, G De Micheli 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 410-416, 2022 | 28 | 2022 |
| Direct model-checking of SysML models AT Calvino, L Apvrille 9th International Conference on Model-Driven Engineering and Software …, 2021 | 14 | 2021 |
| Majority-based design flow for AQFP superconducting family G Meuli, V Possani, R Singh, SY Lee, AT Calvino, DS Marakkalage, ... 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 34-39, 2022 | 13 | 2022 |
| Depth-optimal buffer and splitter insertion and optimization in AQFP circuits AT Calvino, G De Micheli Proceedings of the 28th Asia and South Pacific Design Automation Conference …, 2023 | 12 | 2023 |
| SysML models verification relying on dependency graphs L Apvrille, P de Saqui-Sannes, O Hotescu, AT Calvino 10th International Conference on Model-Driven Engineering and Software …, 2022 | 12 | 2022 |
| Technology Mapping Using Multi-output Library Cells AT Calvino, G De Micheli International Conference on Computer-Aided Design (ICCAD), 2023 | 7 | 2023 |
| Utilizing xmg-based synthesis to preserve self-duality for rfet-based circuits S Rai, AT Calvino, H Riener, G De Micheli, A Kumar IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 7 | 2022 |
| Scalable Logic Rewriting Using Don’t Cares AT Calvino, G De Micheli Proceedings of DATE, 2024 | 5 | 2024 |
| Synthesis of SFQ Circuits with Compound Gates R Bairamkulov, A Tempia Calvino, G De Micheli 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration …, 2023 | 5 | 2023 |
| Improving Standard-Cell Design Flow using Factored Form Optimization AT Calvino, A Mishchenko, H Schmit, E Mahintorabi, G De Micheli, X Xu 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 4 | 2023 |
| From logic to gates: A versatile mapping approach to restructure logic AT Calvino, H Riener, S Rai, GD Micheli Proceedings of the 30th International Workshop on Logic & Synthesis, 2021 | 4 | 2021 |
| Boolean Decomposition Revisited A Mishchenko, R Brayton, A Tempia Calvino, G De Micheli International Workshop on Logic & Synthesis (IWLS), 2023 | 2 | 2023 |
| Enhancing Delay-Driven LUT Mapping with Boolean Decomposition AT Calvino, G De Micheli, A Mishchenko, R Brayton IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | 1 | 2024 |
| Algebraic and Boolean Methods for SFQ Superconducting Circuits AT Calvino, G De Micheli 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 588-593, 2024 | 1 | 2024 |
| In Medio Stat Virtus*: Combining Boolean and Pattern Matching G Radi, A Tempia Calvino, G De Micheli 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 404-410, 2024 | 1 | 2024 |
| Area-Oriented Resubstitution For Networks of Look-Up Tables A Costamagna, AT Calvino, A Mishchenko, G De Micheli IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025 | | 2025 |
| Technology Legalization and Optimization for Adiabatic Quantum-Flux Parametron SY Lee, AT Calvino, H Riener, G De Micheli IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | | 2024 |
| Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration SY Lee, A Tempia Calvino, H Riener, G De Micheli Proceedings of the 61st ACM/IEEE Design Automation Conference, 1-2, 2024 | | 2024 |
| Practical Boolean Decomposition for Delay-driven LUT Mapping AT Calvino, A Mishchenko, G De Micheli, R Brayton arXiv preprint arXiv:2406.06241, 2024 | | 2024 |
Giovanni De MicheliEPFL, Stanford確認したメール アドレス: epfl.ch