| Reduced electric field in junctionless transistors JP Colinge, CW Lee, I Ferain, ND Akhavan, R Yan, P Razavi, R Yu, ... Applied Physics Letters 96 (7), 2010 | 379 | 2010 |
| Junctionless multiple-gate transistors for analog applications RT Doria, MA Pavanello, RD Trevisoli, M de Souza, CW Lee, I Ferain, ... IEEE Transactions on Electron Devices 58 (8), 2511-2519, 2011 | 286 | 2011 |
| Low subthreshold slope in junctionless multigate transistors CW Lee, AN Nazarov, I Ferain, ND Akhavan, R Yan, P Razavi, R Yu, ... Applied Physics Letters 96 (10), 2010 | 285 | 2010 |
| Threshold voltage in junctionless nanowire transistors RD Trevisoli, RT Doria, M de Souza, MA Pavanello Semiconductor Science and Technology 26 (10), 105009, 2011 | 132 | 2011 |
| Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors RD Trevisoli, RT Doria, M de Souza, S Das, I Ferain, MA Pavanello Electron Devices, IEEE Transactions on 59 (12), 3510 - 3518, 2012 | 128 | 2012 |
| Impact of the series resistance in the IV characteristics of junctionless nanowire transistors and its dependence on the temperature RT Doria, RD Trevisoli, M de Souza, MA Pavanello Journal of Integrated Circuits and Systems 7 (2), 121-129, 2012 | 65 | 2012 |
| Cryogenic operation of junctionless nanowire transistors M de Souza, MA Pavanello, RD Trevisoli, RT Doria, JP Colinge IEEE Electron Device Letters 32 (10), 1322-1324, 2011 | 62 | 2011 |
| A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors RD Trevisoli, RT Doria, M de Souza, MA Pavanello Solid-State Electronics 90, 12-17, 2013 | 58 | 2013 |
| Charge-based continuous model for long-channel symmetric double-gate junctionless transistors A Cerdeira, M Estrada, B Iniguez, RD Trevisoli, RT Doria, M De Souza, ... Solid-State Electronics 85, 59-63, 2013 | 48 | 2013 |
| The zero temperature coefficient in junctionless nanowire transistors R Doria Trevisoli, R Trevisoli Doria, M de Souza, S Das, I Ferain, ... Applied Physics Letters 101 (6), 2012 | 40 | 2012 |
| Substrate bias influence on the operation of junctionless nanowire transistors R Trevisoli, RT Doria, M de Souza, MA Pavanello IEEE Transactions on Electron Devices 61 (5), 1575-1582, 2014 | 38 | 2014 |
| Harmonic distortion of unstrained and strained FinFETs operating in saturation RT Doria, A Cerdeira, JA Martino, E Simoen, C Claeys, MA Pavanello IEEE transactions on electron devices 57 (12), 3303-3311, 2010 | 32 | 2010 |
| Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation RT Doria, A Cerdeira, JP Raskin, D Flandre, MA Pavanello Microelectronics journal 39 (12), 1663-1670, 2008 | 32 | 2008 |
| Illuminated to dark ratio improvement in lateral SOI PIN photodiodes at high temperatures C Novo, R Giacomini, R Doria, A Afzalian, D Flandre Semiconductor Science and Technology 29 (7), 075008, 2014 | 29 | 2014 |
| Analysis of the leakage current in junctionless nanowire transistors R Trevisoli, R Trevisoli Doria, M de Souza, M Antonio Pavanello Applied Physics Letters 103 (20), 2013 | 28 | 2013 |
| Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors R Trevisoli, RT Doria, M de Souza, S Barraud, M Vinet, MA Pavanello IEEE Transactions on Electron Devices 63 (2), 856-863, 2016 | 26 | 2016 |
| On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration M de Souza, D Flandre, RT Doria, R Trevisoli, MA Pavanello Solid-State Electronics 117, 152-160, 2016 | 25 | 2016 |
| Analog operation temperature dependence of nMOS junctionless transistors focusing on harmonic distortion RT Doria, MA Pavanello, RD Trevisoli, M de Souza, CW Lee, I Ferain, ... Journal of Integrated Circuits and Systems 6 (2), 114-121, 2011 | 24 | 2011 |
| A new method for series resistance extraction of nanometer MOSFETs R Trevisoli, RT Doria, M de Souza, S Barraud, M Vinet, M Casse, ... IEEE Transactions on Electron Devices 64 (7), 2797-2803, 2017 | 23 | 2017 |
| Junctionless nanowire transistors operation at temperatures down to 4.2 K R Trevisoli, M De Souza, RT Doria, V Kilchtyska, D Flandre, MA Pavanello Semiconductor Science and Technology 31 (11), 114001, 2016 | 22 | 2016 |
Renan TrevisoliPUC-SP確認したメール アドレス: pucsp.br
