| A low noise sub-sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by X Gao, EAM Klumperink, M Bohsali, B Nauta IEEE Journal of Solid-State Circuits 44 (12), 3253-3263, 2009 | 471 | 2009 |
| Jitter analysis and a benchmarking figure-of-merit for phase-locked loops X Gao, EAM Klumperink, PFJ Geraedts, B Nauta IEEE Transactions on Circuits and Systems II: Express Briefs 56 (2), 117-121, 2009 | 283 | 2009 |
| Spur reduction techniques for phase-locked loops exploiting a sub-sampling phase detector X Gao, EAM Klumperink, G Socci, M Bohsali, B Nauta IEEE Journal of Solid-State Circuits 45 (9), 1809-1821, 2010 | 182 | 2010 |
| 9.6 A 2.7-to-4.3 GHz, 0.16 psrms-jitter,− 246.8 dB-FOM, digital fractional-N sampling PLL in 28nm CMOS X Gao, O Burg, H Wang, W Wu, CT Tu, K Manetakis, F Zhang, L Tee, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 174-175, 2016 | 105 | 2016 |
| A 2.2 GHz 7.6 mW sub-sampling PLL with-126dBc/Hz in-band phase noise and 0.15 psrms jitter in 0.18 μm CMOS X Gao, EAM Klumperink, M Bohsali, B Nauta 2009 IEEE International Solid-State Circuits Conference (ISSCC), 2009 | 90 | 2009 |
| Advantages of shift registers over DLLs for flexible low jitter multiphase clock generation X Gao, EAM Klumperink, B Nauta IEEE Transactions on Circuits and Systems II: Express Briefs 55 (3), 244-248, 2008 | 75 | 2008 |
| Sub-sampling PLL techniques X Gao, E Klumperink, B Nauta 2015 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2015 | 56 | 2015 |
| A 2.2 GHz Sub-Sampling PLL with 0.16 psrms Jitter and-125dBc/Hz In-band Phase Noise at 700μW Loop-Components Power X Gao, E Klumperink, G Socci, M Bohsali, B Nauta IEEE Symposium on VLSI Circuits, 139-140, 2010 | 56 | 2010 |
| 9.4 A 2x2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation R Winoto, A Olyaei, M Hajirostam, W Lau, X Gao, A Mitra, O Carnu, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 170-171, 2016 | 53 | 2016 |
| Phase-locked loop including sampling phase detector and charge pump with pulse width control X Gao, EAM Klumperink, B Nauta, M Bohsali, A Kiaei, G Socci, A Djabbari US Patent 7,737,743, 2010 | 47 | 2010 |
| 20.5 A 40nm dual-band 3-stream 802.11 a/b/g/n/ac MIMO WLAN SoC with 1.1 Gb/s over-the-air throughput M He, R Winoto, X Gao, W Loeb, D Signoff, W Lau, Y Lu, D Cui, KS Lee, ... 2014 IEEE International Solid-State Circuits Conference (ISSCC), 350-351, 2014 | 45 | 2014 |
| 9.4 A 28nm CMOS digital fractional-N PLL with− 245.5 dB FOM and a frequency tripler for 802.11 abgn/ac radio X Gao, L Tee, W Wu, KS Lee, AA Paramanandam, A Jha, N Liu, E Chan, ... 2015 IEEE International Solid-State Circuits Conference (ISSCC), 1-3, 2015 | 41 | 2015 |
| All-digital phase locked loop (ADPLL) including a digital-to-time converter (DTC) and a sampling time-to-digital converter (TDC) O Burg, H Wang, X Gao US Patent 9,740,175, 2017 | 34 | 2017 |
| High resolution sampling-based time to digital converter X Gao, CW Yao, CH Lin, L Lin US Patent 8,564,471, 2013 | 29 | 2013 |
| Spur-reduction techniques for PLLs using sub-sampling phase detection X Gao, EAM Klumperink, G Socci, M Bohsali, B Nauta 2010 IEEE International Solid-State Circuits Conference (ISSCC), 2010 | 29 | 2010 |
| Analog fractional-n phase-locked loop H Wang, X Gao, O Burg, CT Tu US Patent App. 15/629,509, 2017 | 20 | 2017 |
| 20.2 A 3.09-to-4.04 GHz distributed-boosting and harmonic-impedance-expanding multi-core oscillator with-138.9 dBc/Hz at 1MHz offset and 195.1 dBc/Hz FoM Y Shu, HJ Qian, X Gao, X Luo 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 296-298, 2021 | 17 | 2021 |
| A low phase noise and high FoM distributed-swing-boosting multi-core oscillator using harmonic-impedance-expanding technique Y Shu, HJ Qian, X Gao, X Luo IEEE Journal of Solid-State Circuits 56 (12), 3728-3740, 2021 | 16 | 2021 |
| Desulfurization characteristic of calcium-based sorbent during activation process X Gao, Z Luo, N Liu, M Ni, K CEN Journal of chemical engineering of Japan 34 (9), 1114-1119, 2001 | 15 | 2001 |
| A 3.3-4.5 GHz fractional-N sampling PLL with a merged constant slope DTC and sampling PD in 40nm CMOS G Jin, F Feng, X Gao, W Chen, Y Shu, X Luo 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 63-66, 2021 | 14 | 2021 |