| A methodology for transistor-efficient supergate design D Kagaris, T Haniotakis IEEE transactions on very large scale integration (VLSI) systems 15 (4), 488-492, 2007 | 62 | 2007 |
| On the use of counters for reproducing deterministic test sets D Kagaris, S Tragoudas, A Majumdar IEEE Transactions on Computers 45 (12), 1405-1419, 1996 | 43 | 1996 |
| On the design of optimal counter-based schemes for test set embedding D Kagaris, S Tragoudas IEEE transactions on computer-aided design of integrated circuits and …, 1999 | 42 | 1999 |
| Partial scan with retiming D Kagaris, S Tragoudas Proceedings of the 30th international Design Automation Conference, 249-254, 1993 | 41 | 1993 |
| A method for pseudo-exhaustive test pattern generation D Kagaris, F Makedon, S Tragoudas IEEE transactions on computer-aided design of integrated circuits and …, 1994 | 38 | 1994 |
| Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms D Kagaris, S Tragoudas, D Karayiannis IEEE transactions on computer-aided design of integrated circuits and …, 1997 | 34 | 1997 |
| Transmissions in a network with capacities and delays D Kagaris, GE Pantziou, S Tragoudas, CD Zaroliagis Networks: An International Journal 33 (3), 167-174, 1999 | 27 | 1999 |
| Using the Berlekamp-Massey algorithm to obtain LFSR characteristic polynomials for TPG O Acevedo, D Kagaris 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2012 | 25 | 2012 |
| Maximum independent sets on transitive graphs and their applications in testing and CAD Kagaris, Tragoudas 1997 Proceedings of IEEE International Conference on Computer Aided Design …, 1997 | 23 | 1997 |
| Generating deterministic unordered test patterns with counters D Kagaris, S Tragoudas Proceedings of 14th VLSI Test Symposium, 374-379, 1996 | 23 | 1996 |
| On the nonenumerative path delay fault simulation problem D Kagaris, S Tragoudas IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2002 | 22 | 2002 |
| On the computation of LFSR characteristic polynomials for built-in deterministic test pattern generation O Acevedo, D Kagaris IEEE Transactions on Computers 65 (2), 664-669, 2015 | 20 | 2015 |
| A unified method for phase shifter computation D Kagaris ACM Transactions on Design Automation of Electronic Systems (TODAES) 10 (1 …, 2005 | 20 | 2005 |
| Retiming-based partial scan D Kagaris, S Tragoudas IEEE transactions on computers 45 (1), 74-87, 1996 | 20 | 1996 |
| Minimizing observation points for fault location S Udar, D Kagaris 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2009 | 18 | 2009 |
| Maximum weighted independent sets on transitive graphs and applications D Kagaris, S Tragoudas Integration 27 (1), 77-86, 1999 | 18 | 1999 |
| Test set embedding based on phase shifters M Bellos, D Kagaris, D Nikolos European Dependable Computing Conference, 90-101, 2002 | 17 | 2002 |
| Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets D Kagaris, S Tragoudas IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1 (4), 526-536, 1993 | 17 | 1993 |
| Detecting VLIW hard errors cost-effectively through a software-based approach A Pillai, W Zhang, D Kagaris 21st International Conference on Advanced Information Networking and …, 2007 | 14 | 2007 |
| Transistor-level optimization of supergates D Kagaris, T Haniotakis 7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-690, 2006 | 14 | 2006 |
