| Six-band calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain, and silicon thickness MV Fischetti, Z Ren, PM Solomon, M Yang, K Rim Journal of Applied Physics 94 (2), 1079-1095, 2003 | 631 | 2003 |
| Silicon device scaling to the sub-10-nm regime M Ieong, B Doris, J Kedzierski, K Rim, M Yang Science 306 (5704), 2057-2060, 2004 | 604 | 2004 |
| High performance CMOS fabricated on hybrid substrate with different crystal orientations M Yang, M Ieong, L Shi, K Chan, V Chan, A Chou, E Gusev, K Jenkins, ... IEEE International Electron Devices Meeting 2003, 18.7. 1-18.7. 4, 2003 | 444 | 2003 |
| Write strategies for 2 and 4-bit multi-level phase-change memory T Nirschl, JB Philipp, TD Happ, GW Burr, B Rajendran, MH Lee, A Schrott, ... 2007 IEEE International Electron Devices Meeting, 461-464, 2007 | 352 | 2007 |
| Ultra thin body fully-depleted SOI MOSFETs BB Doris, M Ieong, Z Ren, PM Solomon, M Yang US Patent 7,459,752, 2008 | 278 | 2008 |
| A 90nm CMOS integrated nano-photonics technology for 25Gbps WDM optical communications applications S Assefa, S Shank, W Green, M Khater, E Kiewra, C Reinholm, ... 2012 International Electron Devices Meeting, 33.8. 1-33.8. 3, 2012 | 239 | 2012 |
| Non-blocking 4x4 electro-optic silicon switch for on-chip photonic networks M Yang, WMJ Green, S Assefa, J Van Campenhout, BG Lee, CV Jahnes, ... Optics express 19 (1), 47-54, 2010 | 238 | 2010 |
| CMOS circuit performance enhancement by surface orientation optimization L Chang, M Ieong, M Yang IEEE Transactions on Electron Devices 51 (10), 1621-1627, 2004 | 228 | 2004 |
| Hybrid-orientation technology (HOT): Opportunities and challenges M Yang, VWC Chan, KK Chan, L Shi, DM Fried, JH Stathis, AI Chou, ... IEEE Transactions on Electron Devices 53 (5), 965-978, 2006 | 225 | 2006 |
| Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics M Yang, EP Gusev, M Ieong, O Gluschenkov, DC Boyd, KK Chan, ... IEEE Electron Device Letters 24 (5), 339-341, 2003 | 203 | 2003 |
| High-performance CMOS devices on hybrid crystal oriented substrates BB Doris, KW Guarini, M Ieong, S Narasimha, K Rim, JW Sleight, M Yang US Patent 7,329,923, 2008 | 195 | 2008 |
| A 25 Gbps silicon microring modulator based on an interleaved junction JC Rosenberg, WMJ Green, S Assefa, DM Gill, T Barwicz, M Yang, ... Optics express 20 (24), 26411-26423, 2012 | 183 | 2012 |
| Hybrid planar and FinFET CMOS devices BB Doris, DC Boyd, M Leong, TS Kanarsky, JT Kedzierski, M Yang US Patent 7,250,658, 2007 | 171 | 2007 |
| Novel lithography-independent pore phase change memory M Breitwisch, T Nirschl, CF Chen, Y Zhu, MH Lee, M Lamorey, GW Burr, ... 2007 IEEE Symposium on VLSI Technology, 100-101, 2007 | 149 | 2007 |
| Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement K Bernstein, JW Sleight, M Yang US Patent 7,605,429, 2009 | 146 | 2009 |
| Hybrid planar and finFET CMOS devices BB Doris, DC Boyd, M Ieong, TS Kanarsky, JT Kedzierski, M Yang US Patent 6,911,383, 2005 | 137 | 2005 |
| CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding M Ieong, A Reznicek, M Yang US Patent 7,023,055, 2006 | 136 | 2006 |
| Silicon device scaling to the sub-10-nm regime M Leong, B Doris, J Kedzierski, K Rim, M Yang Science (Washington, DC) 306 (5704), 2057-2060, 2004 | 131 | 2004 |
| Strained Si CMOS (SS CMOS) technology: opportunities and challenges K Rim, R Anderson, D Boyd, F Cardone, K Chan, H Chen, S Christansen, ... Solid-State Electronics 47 (7), 1133-1139, 2003 | 126 | 2003 |
| Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs BB Doris, M Ieong, EJ Nowak, M Yang US Patent 7,291,886, 2007 | 119 | 2007 |
