| Design issues and considerations for low-cost 3-D TSV IC technology G Van der Plas, P Limaye, I Loi, A Mercha, H Oprins, C Torregiani, S Thijs, ... IEEE Journal of Solid-State Circuits 46 (1), 293-307, 2010 | 397 | 2010 |
| Scalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology E Beyne, SW Kim, L Peng, N Heylen, J De Messemaeker, OO Okudur, ... 2017 IEEE International Electron Devices Meeting (IEDM), 32.4. 1-32.4. 4, 2017 | 162 | 2017 |
| Impact of 3D design choices on manufacturing cost D Velenis, M Stucchi, EJ Marinissen, B Swinnen, E Beyne 2009 IEEE International Conference on 3D System Integration, 1-5, 2009 | 128 | 2009 |
| Test structures for characterization of through-silicon vias M Stucchi, D Perry, G Katti, W Dehaene, D Velenis IEEE transactions on semiconductor manufacturing 25 (3), 355-364, 2012 | 84 | 2012 |
| On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking J Verbree, EJ Marinissen, P Roussel, D Velenis 2010 15th IEEE European Test Symposium, 36-41, 2010 | 69 | 2010 |
| Hybrid 14nm FinFET - Silicon Photonics Technology for Low-Power Tb/s/mm2 Optical I/O M Rakowski, Y Ban, P De Heyn, N Pantano, B Snyder, S Balakrishnan, ... 2018 IEEE Symposium on VLSI Technology, 221-222, 2018 | 66 | 2018 |
| Ultra-fine pitch 3D integration using face-to-face hybrid wafer bonding combined with a via-middle through-silicon-via process SW Kim, M Detalle, L Peng, P Nolmans, N Heylen, D Velenis, A Miller, ... 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 1179-1185, 2016 | 65 | 2016 |
| Implementation of an industry compliant, 5× 50μm, via-middle TSV technology on 300mm wafers A Redolfi, D Velenis, S Thangaraju, P Nolmans, P Jaenen, M Kostermans, ... 2011 IEEE 61st Electronic Components and Technology Conference (ECTC), 1384-1388, 2011 | 60 | 2011 |
| Temperature-dependent modeling and characterization of through-silicon via capacitance G Katti, M Stucchi, D Velenis, B Soree, K De Meyer, W Dehaene IEEE Electron Device Letters 32 (4), 563-565, 2011 | 52 | 2011 |
| Temperature dependent electrical characteristics of through-si-via (TSV) interconnections G Katti, A Mercha, M Stucchi, Z Tokei, D Velenis, J Van Olmen, ... 2010 IEEE International Interconnect Technology Conference, 1-3, 2010 | 42 | 2010 |
| Cost effectiveness of 3D integration options D Velenis, EJ Marinissen, E Beyne 2010 IEEE International 3D Systems Integration Conference (3DIC), 1-6, 2010 | 38 | 2010 |
| Active-lite interposer for 2.5 & 3D integration G Hellings, M Scholz, M Detalle, D Velenis, MP de ten Broeck, CR Neve, ... 2015 Symposium on VLSI Circuits (VLSI Circuits), T222-T223, 2015 | 33 | 2015 |
| Enhanced barrier seed metallization for integration of high-density high aspect-ratio copper-filled 3D through-silicon via interconnects Y Civale, S Armini, H Philipsen, A Redolfi, D Velenis, K Croes, N Heylen, ... 2012 IEEE 62nd electronic components and technology conference, 822-826, 2012 | 30 | 2012 |
| Challenges and improvements for 3D-IC integration using ultra thin (25μm) devices A La Manna, T Buisson, M Detalle, KJ Rebibis, D Velenis, W Zhang, ... 2012 IEEE 62nd Electronic Components and Technology Conference, 532-536, 2012 | 27 | 2012 |
| Electrical characterization method to study barrier integrity in 3D through-silicon vias YL Li, D Velenis, T Kauerauf, M Stucchi, Y Civale, A Redolfi, K Croes 2012 IEEE 62nd Electronic Components and Technology Conference, 304-308, 2012 | 27 | 2012 |
| Impact of thinning and through silicon via proximity on high-k/metal gate first CMOS performance A Mercha, A Redolfi, M Stucchi, N Minas, J Van Olmen, S Thangaraju, ... 2010 Symposium on VLSI Technology, 109-110, 2010 | 27 | 2010 |
| Imec silicon photonics platforms: performance overview and roadmap FJ Ferraro, P De Heyn, M Kim, N Rajasekaran, M Berciano, G Muliuk, ... Next-Generation Optical Communication: Components, Sub-Systems, and Systems …, 2023 | 26 | 2023 |
| High-speed TSV integration in an active silicon photonics interposer platform L Bogaerts, Z El-Mekki, S Van Huylenbroeck, P Nolmans, N Pantano, ... 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018 | 17 | 2018 |
| High density and high bandwidth chip-to-chip connections with 20μm pitch flip-chip on fan-out wafer level package D Velenis, A Phommahaxay, P Bex, F Fodor, EJ Marinissen, K Rebibis, ... 2018 International Wafer Level Packaging Conference (IWLPC), 1-5, 2018 | 16 | 2018 |
| Technology Assessment of Through-Silicon Via by Using–and–Measurements G Katti, M Stucchi, D Velenis, S Thangaraju, K De Meyer, W Dehaene, ... IEEE electron device letters 32 (7), 946-948, 2011 | 16 | 2011 |