| Accelerating binarized convolutional neural networks with software-programmable FPGAs R Zhao, W Song, W Zhang, T Xing, JH Lin, M Srivastava, R Gupta, ... Proceedings of the 2017 ACM/SIGDA international symposium on field …, 2017 | 519 | 2017 |
| Serving dnns in real time at datacenter scale with project brainwave E Chung, J Fowers, K Ovtcharov, M Papamichael, A Caulfield, ... iEEE Micro 38 (2), 8-20, 2018 | 409 | 2018 |
| Improving neural network quantization without retraining using outlier channel splitting R Zhao, Y Hu, J Dotzel, C De Sa, Z Zhang International conference on machine learning, 7543-7552, 2019 | 371 | 2019 |
| Rosetta: A realistic high-level synthesis benchmark suite for software programmable FPGAs Y Zhou, U Gupta, S Dai, R Zhao, N Srivastava, H Jin, J Featherston, ... Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018 | 161 | 2018 |
| The Celerity open-source 511-core RISC-V tiered accelerator fabric: Fast architectures and design methodologies for fast chips S Davidson, S Xie, C Torng, K Al-Hawai, A Rovinski, T Ajayi, L Vega, ... IEEE Micro 38 (2), 30-41, 2018 | 134 | 2018 |
| Pushing the limits of narrow precision inferencing at cloud scale with microsoft floating point B Darvish Rouhani, D Lo, R Zhao, M Liu, J Fowers, K Ovtcharov, ... Advances in neural information processing systems 33, 10271-10281, 2020 | 133 | 2020 |
| Accelerating persistent neural networks at datacenter scale E Chung, J Fowers, K Ovtcharov, M Papamichael, A Caulfield, ... Hot Chips 29, 2017 | 86 | 2017 |
| Quantization for dnn accelerators DC Burger, ES Chung, BD Rouhani, D Lo, R Zhao US Patent App. 15/972,048, 2019 | 73 | 2019 |
| Flow for quantized neural networks DC Burger, ES Chung, BD Rouhani, D Lo, R Zhao US Patent 11,645,493, 2023 | 70 | 2023 |
| Elasticflow: A complexity-effective approach for pipelining irregular loop nests M Tan, G Liu, R Zhao, S Dai, Z Zhang 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 78-85, 2015 | 63 | 2015 |
| A parallel bandit-based approach for autotuning FPGA compilation C Xu, G Liu, R Zhao, S Yang, G Luo, Z Zhang Proceedings of the 2017 ACM/SIGDA international symposium on field …, 2017 | 62 | 2017 |
| Microscaling data formats for deep learning BD Rouhani, R Zhao, A More, M Hall, A Khodamoradi, S Deng, ... arXiv preprint arXiv:2310.10537, 2023 | 53 | 2023 |
| Adjusting activation compression for neural network training D Lo, BD Rouhani, ES Chung, Y Zhao, A Phanishayee, R Zhao US Patent App. 16/276,395, 2020 | 51 | 2020 |
| Dynamic hazard resolution for pipelining irregular loops in high-level synthesis S Dai, R Zhao, G Liu, S Srinath, U Gupta, C Batten, Z Zhang Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017 | 43 | 2017 |
| With shared microexponents, a little shifting goes a long way B Darvish Rouhani, R Zhao, V Elango, R Shafipour, M Hall, ... Proceedings of the 50th Annual International Symposium on Computer …, 2023 | 42 | 2023 |
| Celerity: An open source RISC-V tiered accelerator fabric T Ajayi, K Al-Hawaj, A Amarnath, S Dai, S Davidson, P Gao, G Liu, A Lotfi, ... Symp. on High Performance Chips (Hot Chips), 2017 | 38 | 2017 |
| Binarized convolutional neural networks with separable filters for efficient hardware acceleration JH Lin, T Xing, R Zhao, Z Zhang, M Srivastava, Z Tu, RK Gupta Proceedings of the IEEE Conference on Computer Vision and Pattern …, 2017 | 38 | 2017 |
| A 1.4 GHz 695 Giga Risc-V inst/s 496-core manycore processor with mesh on-chip network and an all-digital synthesized PLL in 16nm CMOS A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ... 2019 Symposium on VLSI Circuits, C30-C31, 2019 | 35 | 2019 |
| Building efficient deep neural networks with unitary group convolutions R Zhao, Y Hu, J Dotzel, CD Sa, Z Zhang Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern …, 2019 | 34 | 2019 |
| Evaluating celerity: A 16-nm 695 Giga-RISC-V instructions/s manycore processor with synthesizable PLL A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ... IEEE Solid-State Circuits Letters 2 (12), 289-292, 2019 | 33 | 2019 |
Zhiru ZhangCornell University確認したメール アドレス: cornell.edu