Another look at LTL model checking E Clarke, O Grumberg, K Hamaguchi Computer Aided Verification: 6th International Conference, CAV'94 Stanford …, 1994 | 241 | 1994 |
Another look at LTL model checking EM Clarke, O Grumberg, K Hamaguchi Formal Methods in System Design 10, 47-71, 1997 | 228 | 1997 |
The complexity of the optimal variable ordering problems of a shared binary decision diagram S Tani, K Hamaguchi, S Yajima IEICE TRANSACTIONS on Information and Systems 79 (4), 271-281, 1996 | 183 | 1996 |
Efficient construction of binary moment diagrams for verifying arithmetic circuits K Hamaguchi, A Morita, S Yajima Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995 | 93 | 1995 |
Ordered quantum branching programs are more powerful than ordered probabilistic branching programs under a bounded-width restriction M Nakanishi, K Hamaguchi, T Kashiwabara Computing and Combinatorics: 6th Annual International Conference, COCOON …, 2000 | 69 | 2000 |
Symbolic simulation heuristics for high-level design descriptions with uninterpreted functions K Hamaguchi Sixth IEEE International High-Level Design Validation and Test Workshop, 25-30, 2001 | 15 | 2001 |
Design verification of asynchronous sequential circuits using symbolic model checking K Hamaguchi Proc. Int'l Symp. Logic Synthesis and Microprocessor Architecture, 84-90, 1992 | 15 | 1992 |
Branching time regular temporal logic for model checking with linear time complexity K Hamaguchi, H Hiraishi, S Yajima Computer-Aided Verification: 2nd International Conference, CAV'90 New …, 1991 | 14 | 1991 |
Symbolic checking of signal-transition consistency for verifying high-level designs K Hamaguchi, H Urushihara, T Kashiwabara Formal Methods in Computer-Aided Design: Third International Conference …, 2000 | 13 | 2000 |
On the power of non-deterministic quantum finite automata M Nakanishi, T Indoh, K Hamaguchi, T Kashiwabara IEICE TRANSACTIONS on Information and Systems 85 (2), 327-332, 2002 | 12 | 2002 |
Vectorized symbolic model checking of computation tree logic for sequential machine verification H Hiraishi, K Hamaguchi, H Ochi, S Yajima Computer Aided Verification: 3rd International Workshop, CAV'91 Aalborg …, 1992 | 11 | 1992 |
Expressive power of quantum pushdown automata with classical stack operations under the perfect-soundness condition M Nakanishi, K Hamaguchi, T Kashiwabara IEICE transactions on information and systems 89 (3), 1120-1127, 2006 | 7 | 2006 |
Formal verification of speed-dependent asynchronous circuits using symbolic model checking of branching time regular temporal logic K Hamaguchi, H Hiraishi, S Yajima Computer Aided Verification: 3rd International Workshop, CAV'91 Aalborg …, 1992 | 7 | 1992 |
Compact test sequences for scan-based sequential circuits H Higuchi, K Hamaguchi, S Yajima IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and …, 1993 | 6 | 1993 |
Automatic monitor generation from regular expression based specifications for module interface verification Y Kakiuchi, A Kitajima, K Hamaguchi, T Kashiwabara 2005 IEEE International Symposium on Circuits and Systems (ISCAS), 3555-3558, 2005 | 5 | 2005 |
On the power of quantum pushdown automata with a classical stack and 1.5-way quantum finite automata M Nakanishi, T Indoh, K Hamaguchi, T Kashiwabara Information Science Technical Report, 2001 | 5 | 2001 |
Manipulation of large-scale polynomials using BMDs D ROTTER, K HAMAGUCHI, S MINATO, S YAJIMA IEICE transactions on fundamentals of electronics, communications and …, 1997 | 5 | 1997 |
Exponential Lower Bounds of the Sizes of Binary Moment Diagrams Representing Division. M NAKANISHI, K HAMAGUCHI, T KASHIWABARA 電子情報通信学会技術研究報告 97 (356 (COMP97 45-59)), 63-70, 1997 | 5 | 1997 |
Design verification of a microprocessor using branching time regular temporal logic K Hamaguchi, H Hiraishi, S Yajima Computer Aided Verification: Fourth International Workshop, CAV'92 Montreal …, 1993 | 5 | 1993 |
Satisfiability checking for logic with equality and uninterpreted functions under equivalence constraints H Kozawa, K Hamaguchi, T Kashiwabara IEICE transactions on fundamentals of electronics, communications and …, 2007 | 4 | 2007 |