| Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance KA Bowman, JW Tschanz, NS Kim, JC Lee, CB Wilkerson, SLL Lu, ... IEEE Journal of Solid-State Circuits 44 (1), 49-63, 2008 | 457 | 2008 |
| Trading off cache capacity for reliability to enable low voltage operation C Wilkerson, H Gao, AR Alameldeen, Z Chishti, M Khellah, SL Lu ACM SIGARCH computer architecture news 36 (3), 203-214, 2008 | 380 | 2008 |
| A 45 nm resilient microprocessor core for dynamic variation tolerance KA Bowman, JW Tschanz, SLL Lu, PA Aseron, MM Khellah, ... IEEE Journal of Solid-State Circuits 46 (1), 194-208, 2010 | 341 | 2010 |
| Floating-body dynamic random access memory and method of fabrication in tri-gate technology SH Tang, A Keshavarzi, D Somasekhar, F Paillet, MM Khellah, Y Ye, ... US Patent 7,098,507, 2006 | 331 | 2006 |
| Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM MT Chang, P Rosenfeld, SL Lu, B Jacob 2013 IEEE 19th international symposium on high performance computer …, 2013 | 302 | 2013 |
| Speeding up processing with approximation circuits SL Lu Computer 37 (3), 67-73, 2004 | 302 | 2004 |
| Reducing cache power with low-cost, multi-bit error-correcting codes C Wilkerson, AR Alameldeen, Z Chishti, W Wu, D Somasekhar, S Lu Proceedings of the 37th annual international symposium on Computer …, 2010 | 296 | 2010 |
| RAMP: Research accelerator for multiple processors J Wawrzynek, D Patterson, M Oskin, SL Lu, C Kozyrakis, JC Hoe, D Chiou, ... IEEE micro 27 (2), 46-57, 2007 | 231 | 2007 |
| Energy-efficient cache design using variable-strength error-correcting codes AR Alameldeen, I Wagner, Z Chishti, W Wu, C Wilkerson, SL Lu ACM SIGARCH Computer Architecture News 39 (3), 461-472, 2011 | 227 | 2011 |
| Improving cache lifetime reliability at ultra-low voltages Z Chishti, AR Alameldeen, C Wilkerson, W Wu, SL Lu Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009 | 219 | 2009 |
| Coming challenges in microarchitecture and architecture R Ronen, A Mendelson, K Lai, SL Lu, F Pollack, JP Shen Proceedings of the IEEE 89 (3), 325-340, 2001 | 216 | 2001 |
| STTRAM SCALING AND RETENTION FAILURE. H Naeimi, C Augustine, A Raychowdhury, SL Lu, J Tschanz intel technology journal 17 (1), 2013 | 204 | 2013 |
| Circuit techniques for dynamic variation tolerance K Bowman, J Tschanz, C Wilkerson, SL Lu, T Karnik, V De, S Borkar Proceedings of the 46th Annual Design Automation Conference, 4-7, 2009 | 169 | 2009 |
| DRAM refresh mechanisms, penalties, and trade-offs I Bhati, MT Chang, Z Chishti, SL Lu, B Jacob IEEE Transactions on Computers 65 (1), 108-121, 2015 | 165 | 2015 |
| Sandbox prefetching: Safe run-time evaluation of aggressive prefetchers SH Pugsley, Z Chishti, C Wilkerson, P Chuang, RL Scott, A Jaleel, SL Lu, ... 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 150 | 2014 |
| Floating-body memory cell write SH Tang, A Keshavarzi, D Somasekhar, F Paillet, MM Khellah, Y Ye, ... US Patent 7,061,806, 2006 | 136 | 2006 |
| Bloom filtering cache misses for accurate data speculation and prefetching JK Peir, SC Lai, SL Lu, J Stark, K Lai ACM International Conference on Supercomputing 25th Anniversary Volume, 347-356, 2002 | 136 | 2002 |
| Flexible auto-refresh: Enabling scalable and energy-efficient DRAM refresh reductions I Bhati, Z Chishti, SL Lu, B Jacob Proceedings of the 42nd Annual International Symposium on Computer …, 2015 | 134 | 2015 |
| Noise suppression for open bit line DRAM architectures D Somasekhar, SL Lu, VK De US Patent 6,721,222, 2004 | 127 | 2004 |
| One-transistor and one-capacitor DRAM cell for logic process technology SLL Lu, VK De US Patent 6,359,802, 2002 | 123 | 2002 |
Vivek DeIntel Fellow, Intel Corporation確認したメール アドレス: intel.com