フォロー
Joshua San Miguel
Joshua San Miguel
Associate Professor, Department of Electrical and Computer Engineering, University of Wisconsin
確認したメール アドレス: wisc.edu - ホームページ
タイトル
引用先
引用先
年
Load value approximation
J San Miguel, M Badr, NE Jerger
2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 127-139, 2014
2272014
Load value approximation: Approaching the ideal memory access latency
J San Miguel, NE Jerger
Workshop on Approximate Computing Across the System Stack, 2014
227*2014
Doppelgänger: a cache for approximate computing
JS Miguel, J Albericio, A Moshovos, NE Jerger
Proceedings of the 48th International Symposium on Microarchitecture, 50-61, 2015
1712015
The bunker cache for spatio-value approximation
J San Miguel, J Albericio, NE Jerger, A Jaleel
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
722016
A taxonomy of general purpose approximate computing techniques
T Moreau, J San Miguel, M Wyse, J Bornholt, A Alaghi, L Ceze, NE Jerger, ...
IEEE Embedded Systems Letters 10 (1), 2-5, 2017
662017
A Taxonomy of Approximate Computing Techniques
T Moreau, J San Miguel, M Wyse, J Bornholt, L Ceze, NE Jerger, ...
66*2016
UGEMM: Unary Computing Architecture for GEMM Applications
D Wu, J Li, R Yin, H Hsiao, Y Kim, J San Miguel
2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020
552020
The Anytime Automaton
J San Miguel, NE Jerger
46*2016
The What’s Next Intermittent Computing Architecture
K Ganesan, J San Miguel, NE Jerger
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
382019
Texture Cache Approximation on GPUs
M Sutherland, J San Miguel, NE Jerger
382015
The EH Model: Early Design Space Exploration of Intermittent Processor Architectures
J San Miguel, K Ganesan, M Badr, C Xia, R Li, H Hsiao, NE Jerger
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
372018
The runahead network-on-chip
Z Li, J San Miguel, NE Jerger
2016 IEEE International Symposium on High Performance Computer Architecture …, 2016
352016
The inner most loop iteration counter: a new dimension in branch history
A Seznec, JS Miguel, J Albericio
Proceedings of the 48th International Symposium on Microarchitecture, 347-357, 2015
35*2015
DRAIN: Deadlock Removal for Arbitrary Irregular Networks
M Parasar, H Farrokhbakht, NE Jerger, PV Gratz, T Krishna, J San Miguel
2020 IEEE International Symposium on High Performance Computer Architecture …, 2020
342020
SWAP: Synchronized Weaving of Adjacent Packets for Network Deadlock Resolution
M Parasar, NE Jerger, PV Gratz, JS Miguel, T Krishna
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
302019
The EH model: Analytical exploration of energy-harvesting architectures
J San Miguel, K Ganesan, M Badr, NE Jerger
IEEE Computer Architecture Letters 17 (1), 76-79, 2017
302017
SECO: A Scalable Accuracy Approximate Exponential Function Via Cross-Layer Optimization
D Wu, T Chen, C Chen, O Ahia, J San Miguel, M Lipasti, Y Kim
2019 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2019
272019
In-stream stochastic division and square root via correlation
D Wu, JS Miguel
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
262019
Pitstop: Enabling a Virtual Network Free Network-on-Chip
H Farrokhbakht, H Kao, K Hasan, PV Gratz, T Krishna, J San Miguel, ...
2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021
252021
Data criticality in network-on-chip design
JS Miguel, NE Jerger
Proceedings of the 9th International Symposium on Networks-on-Chip, 1-8, 2015
232015
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