Exploring eFPGA-based redaction for IP protection J Bhandari, AKT Moosa, B Tan, C Pilato, G Gore, X Tang, S Temple, ... 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 44 | 2021 |
Not all fabrics are created equal: Exploring eFPGA parameters for IP redaction J Bhandari, AKT Moosa, B Tan, C Pilato, G Gore, X Tang, S Temple, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023 | 26 | 2023 |
ALICE: An automatic design flow for eFPGA redaction CM Tomajoli, L Collini, J Bhandari, AKT Moosa, B Tan, X Tang, ... Proceedings of the 59th ACM/IEEE Design Automation Conference, 781-786, 2022 | 20 | 2022 |
FastSim: A fast simulation framework for high-level synthesis M Abderehman, J Patidar, J Oza, Y Nigam, TMA Khader, C Karfa IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 19 | 2021 |
HOST: HLS obfuscations against SMT attack C Karfa, TMA Khader, Y Nigam, R Chouksey, R Karri 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 32-37, 2021 | 9 | 2021 |
Improving lifetime of non-volatile memory caches by logical partitioning S Sivakumar, TM Abdul Khader, J Jose Proceedings of the 2021 on Great Lakes Symposium on VLSI, 123-128, 2021 | 6 | 2021 |
Imagespec: Efficient high-level synthesis of image processing applications AKT Moosa, N Sarma, C Karfa 2022 25th Euromicro Conference on Digital System Design (DSD), 67-74, 2022 | 5 | 2022 |
Scaling Attacks on Large Logic-Locked Designs AKT Moosa, B Tan, R Karri IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 | 1 | 2023 |