| A quantitative analysis on microarchitectures of modern CPU-FPGA platforms Y Choi, J Cong, Z Fang, Y Hao, G Reinman, P Wei Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 193 | 2016 |
| Hbm connect: High-performance hls interconnect for fpga hbm Y Choi, Y Chi, W Qiao, N Samardzic, J Cong The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays …, 2021 | 82 | 2021 |
| Sextans: A streaming accelerator for general-purpose sparse-matrix dense-matrix multiplication L Song, Y Chi, A Sohrabizadeh, Y Choi, J Lau, J Cong Proceedings of the 2022 ACM/SIGDA International Symposium on Field …, 2022 | 74* | 2022 |
| Extending high-level synthesis for task-parallel programs Y Chi, L Guo, J Lau, Y Choi, J Wang, J Cong 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom …, 2021 | 61 | 2021 |
| HLScope+: Fast and accurate performance estimation for FPGA HLS Y Choi, P Zhang, P Li, J Cong 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 691-698, 2017 | 58 | 2017 |
| In-depth analysis on microarchitectures of modern heterogeneous CPU-FPGA platforms YK Choi, J Cong, Z Fang, Y Hao, G Reinman, P Wei ACM Transactions on Reconfigurable Technology and Systems (TRETS) 12 (1), 1-20, 2019 | 56 | 2019 |
| A real-time FPGA-based 20 000-word speech recognizer with optimized DRAM access YK Choi, K You, J Choi, W Sung IEEE Transactions on Circuits and Systems I: Regular Papers 57 (8), 2119-2131, 2010 | 50 | 2010 |
| HLS-based optimization and design space exploration for applications with variable loop bounds Y Choi, J Cong 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 47 | 2018 |
| HLScope: High-level performance debugging for FPGA designs Y Choi, J Cong 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom …, 2017 | 42 | 2017 |
| When hls meets fpga hbm: Benchmarking and bandwidth optimization Y Choi, Y Chi, J Wang, L Guo, J Cong arXiv preprint arXiv:2010.06075, 2020 | 36* | 2020 |
| FLASH: Fast, parallel, and accurate simulator for HLS YK Choi, Y Chi, J Wang, J Cong IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 32 | 2020 |
| Acceleration of EM-based 3D CT reconstruction using FPGA Y Choi, J Cong IEEE transactions on biomedical circuits and systems 10 (3), 754-767, 2015 | 29 | 2015 |
| Rapid cycle-accurate simulator for high-level synthesis Y Chi, Y Choi, J Cong, J Wang Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019 | 21 | 2019 |
| VLSI for 5000-word continuous speech recognition Y Choi, K You, J Choi, W Sung IEEE International Conference on Acoustics, Speech and Signal Processing …, 2009 | 15 | 2009 |
| FPGA implementation of EM algorithm for 3D CT reconstruction YK Choi, J Cong, D Wu 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom …, 2014 | 14* | 2014 |
| FPGA-based implementation of a real-time 5000-word continuous speech recognizer Y Choi, K You, W Sung 2008 16th European Signal Processing Conference, 1-5, 2008 | 13 | 2008 |
| Memory access optimized VLSI for 5000-word continuous speech recognition K You, Y Choi, J Choi, W Sung Journal of Signal Processing Systems 63, 95-105, 2011 | 12 | 2011 |
| Efficient GPU-based graph cuts for stereo matching Y Choi, I Park Proceedings of the IEEE Conference on Computer Vision and Pattern …, 2013 | 9 | 2013 |
| FPGA acceleration of probabilistic sentential decision diagrams with high-level synthesis Y Choi, C Santillana, Y Shen, A Darwiche, J Cong ACM Transactions on Reconfigurable Technology and Systems 16 (2), 1-22, 2023 | 8 | 2023 |
| Taro: Automatic optimization for free-running kernels in fpga high-level synthesis YK Choi, Y Chi, J Lau, J Cong IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 5 | 2022 |
Jingsheng Jason CongVolgenau Chair for Engineering Excellence, Computer Science and Electrical Engineering, University確認したメール アドレス: cs.ucla.edu