| Performance optimization using variable-latency design style YS Su, DC Wang, SC Chang, M Marek-Sadowska IEEE transactions on very large scale integration (VLSI) systems 19 (10 …, 2010 | 62 | 2010 |
| Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs YS Su, WK Hon, CC Yang, SC Chang, YJ Chang Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009 | 40 | 2009 |
| Clock skew minimization in multi-voltage mode designs using adjustable delay buffers YS Su, WK Hon, CC Yang, SC Chang, YJ Chang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 35 | 2010 |
| An efficient mechanism for performance optimization of variable-latency designs YS Su, DC Wang, SC Chang, M Marek-Sadowska Proceedings of the 44th annual Design Automation Conference, 976-981, 2007 | 30 | 2007 |
| Through-silicon via fault-tolerant clock networks for 3-D ICs CL Lung, YS Su, HH Huang, Y Shi, SC Chang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 29 | 2013 |
| Fault-tolerant 3D clock network CL Lung, YS Su, SH Huang, Y Shi, SC Chang Proceedings of the 48th Design Automation Conference, 645-651, 2011 | 27 | 2011 |
| Fault-tolerant unit and method for through-silicon via CL Lung, YS Su, SC Chang, Y Shi US Patent 9,177,940, 2015 | 20 | 2015 |
| Benchmarking for research in power delivery networks of three-dimensional integrated circuits PW Luo, C Zhang, YT Chang, LC Cheng, HH Lee, BL Sheu, YS Su, ... Proceedings of the 2013 ACM International symposium on Physical Design, 17-24, 2013 | 11 | 2013 |
| Capturing the phantom of the power grid-on the runtime adaptive techniques for noise reduction T Wang, PW Luo, YS Su, LC Cheng, DM Kwai, Y Shi 17th Asia and South Pacific Design Automation Conference, 640-645, 2012 | 6 | 2012 |
| Synthesis of a novel timing-error detection architecture YS Su, PH Chang, SC Chang, T Hwang ACM Transactions on Design Automation of Electronic Systems (TODAES) 13 (1 …, 2008 | 5 | 2008 |
| Efficient calculation of timed cumulative probability density function YS Su, YH Weng, SC Chang 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2007 | 1 | 2007 |
| Synthesis of a timing-error detection architecture YS Su, PH Chang, SC Chang, TT Hwang 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI …, 2008 | | 2008 |
