| In-memory computing: Advances and prospects N Verma, H Jia, H Valavi, Y Tang, M Ozatay, LY Chen, B Zhang, ... IEEE solid-state circuits magazine 11 (3), 43-55, 2019 | 406 | 2019 |
| A 64-tile 2.4-Mb in-memory-computing CNN accelerator employing charge-domain compute H Valavi, PJ Ramadge, E Nestler, N Verma IEEE Journal of Solid-State Circuits 54 (6), 1789-1799, 2019 | 335 | 2019 |
| A programmable heterogeneous microprocessor based on bit-scalable in-memory computing H Jia, H Valavi, Y Tang, J Zhang, N Verma IEEE Journal of Solid-State Circuits 55 (9), 2609-2621, 2020 | 195 | 2020 |
| A mixed-signal binarized convolutional-neural-network accelerator integrating dense weight storage and multiplication for reduced data movement H Valavi, PJ Ramadge, E Nestler, N Verma 2018 IEEE Symposium on VLSI Circuits, 141-142, 2018 | 175 | 2018 |
| 15.1 a programmable neural-network inference accelerator based on scalable in-memory computing H Jia, M Ozatay, Y Tang, H Valavi, R Pathak, J Lee, N Verma 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 236-238, 2021 | 158* | 2021 |
| Scalable and programmable neural network inference accelerator based on in-memory computing H Jia, M Ozatay, Y Tang, H Valavi, R Pathak, J Lee, N Verma IEEE Journal of Solid-State Circuits 57 (1), 198-211, 2021 | 84 | 2021 |
| Fully row/column-parallel in-memory computing SRAM macro employing capacitor-based mixed-signal computation with 5-b inputs J Lee, H Valavi, Y Tang, N Verma 2021 Symposium on VLSI Circuits, 1-2, 2021 | 78 | 2021 |
| A microprocessor implemented in 65nm CMOS with configurable and bit-scalable accelerator for programmable in-memory computing H Jia, Y Tang, H Valavi, J Zhang, N Verma arXiv preprint arXiv:1811.04047, 2018 | 45 | 2018 |
| Analog switched-capacitor neural network EG Nestler, N Verma, H Valavi US Patent 11,263,522, 2022 | 32 | 2022 |
| Configurable in memory computing engine, platform, bit cells and layouts therefore N Verma, H Valavi, H Jia US Patent 11,669,446, 2023 | 19 | 2023 |
| A Programmable Embedded Microprocessor for Bit-scalable In-memory Computing. H Jia, H Valavi, Y Tang, J Zhang, N Verma Hot Chips Symposium, 1-29, 2019 | 14 | 2019 |
| Revisiting the landscape of matrix factorization H Valavi, S Liu, P Ramadge International Conference on Artificial Intelligence and Statistics, 1629-1638, 2020 | 5 | 2020 |
| The landscape of matrix factorization revisited H Valavi, S Liu, PJ Ramadge arXiv preprint arXiv:2002.12795, 2020 | 4 | 2020 |
| Scalable array architecture for in-memory computing H Jia, M Ozatay, H Valavi, N Verma US Patent App. 17/797,833, 2023 | 3 | 2023 |
| Multi-dataset low-rank matrix factorization H Valavi, PJ Ramadge 2019 53rd Annual Conference on Information Sciences and Systems (CISS), 1-5, 2019 | 2 | 2019 |
| An upper-bound on the required size of a neural network classifier H Valavi, PJ Ramadge 2018 IEEE International Conference on Acoustics, Speech and Signal …, 2018 | 2 | 2018 |
| Configurable in memory computing engine, platform, bit cells and layouts therefore N Verma, H Valavi, H Jia US Patent 12,007,890, 2024 | 1 | 2024 |
| Hardware Acceleration to Address the Costs of Data Movement H Valavi https://pqdtopen.proquest.com/pubnum/27548046.html, 2020 | 1 | 2020 |
| Configurable in memory computing engine, platform, bit cells and layouts therefore N Verma, H Valavi, H Jia US Patent App. 18/738,851, 2024 | | 2024 |
| Analog switched-capacitor neural network EG Nestler, N Verma, H Valavi US Patent 12,061,977, 2024 | | 2024 |