| A 3.1 mW 8b 1.2 GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS L Kull, T Toifl, M Schmatz, PA Francese, C Menolfi, M Braendli, M Kossel, ... IEEE Journal of Solid-State Circuits 48 (12), 3049-3058, 2013 | 431 | 2013 |
| Temporal correlation detection using computational phase-change memory A Sebastian, T Tuma, N Papandreou, M Le Gallo, L Kull, T Parnell, ... Nature Communications 8 (1), 1115, 2017 | 266 | 2017 |
| 22.1 a 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS L Kull, T Toifl, M Schmatz, PA Francese, C Menolfi, M Braendli, M Kossel, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 231 | 2014 |
| A 24–72-GS/s 8-b time-interleaved SAR ADC with 2.0–3.3-pJ/conversion and> 30 dB SNDR at Nyquist in 14-nm CMOS FinFET L Kull, D Luu, C Menolfi, M Braendli, PA Francese, T Morf, M Kossel, ... IEEE Journal of Solid-State Circuits 53 (12), 3508-3516, 2018 | 139 | 2018 |
| 28.5 A 10b 1.5 GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET L Kull, D Luu, C Menolfi, M Braendli, PA Francese, T Morf, M Kossel, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 474-475, 2017 | 107 | 2017 |
| A 4.6W/mm2power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS TM Andersen, F Krismer, JW Kolar, T Toifl, C Menolfi, L Kull, T Morf, ... 2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and …, 2013 | 101 | 2013 |
| Implementation of low-power 6–8 b 30–90 GS/s time-interleaved ADCs with optimized input bandwidth in 32 nm CMOS L Kull, J Pliva, T Toifl, M Schmatz, PA Francese, C Menolfi, M Braendli, ... IEEE Journal of Solid-State Circuits 51 (3), 636-648, 2016 | 98 | 2016 |
| A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7 W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS TM Andersen, F Krismer, JW Kolar, T Toifl, C Menolfi, L Kull, T Morf, ... IEEE International Solid-State Circuits Conference, 2014 | 97 | 2014 |
| A 112Gb/S 2.6 pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS C Menolfi, M Braendli, PA Francese, T Morf, A Cevrero, M Kossel, L Kull, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 104-106, 2018 | 79 | 2018 |
| 6.1 A 100Gb/s 1.1 pJ/b PAM-4 RX with dual-mode 1-tap PAM-4/3-tap NRZ speculative DFE in 14nm CMOS FinFET A Cevrero, I Ozkaya, PA Francese, M Brandli, C Menolfi, T Morf, M Kossel, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 112-114, 2019 | 76 | 2019 |
| A 64-Gb/s 1.4-pJ/b NRZ optical receiver data-path in 14-nm CMOS FinFET I Ozkaya, A Cevrero, PA Francese, C Menolfi, T Morf, M Brändli, ... IEEE Journal of Solid-State Circuits 52 (12), 3458-3473, 2017 | 76 | 2017 |
| A 10 W on-chip switched capacitor voltage regulator with feedforward regulation capability for granular microprocessor power delivery TM Andersen, F Krismer, JW Kolar, T Toifl, C Menolfi, L Kull, T Morf, ... IEEE Transactions on Power Electronics 32 (1), 378-393, 2016 | 67 | 2016 |
| A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS L Kull, T Toifl, M Schmatz, PA Francese, C Menolfi, M Braendli, M Kossel, ... 2013 Symposium on VLSI Circuits, C260-C261, 2013 | 66 | 2013 |
| A 161-mW 56-Gb/s ADC-based discrete multitone wireline receiver data-path in 14-nm FinFET G Kim, L Kull, D Luu, M Braendli, C Menolfi, PA Francese, H Yueksel, ... IEEE Journal of Solid-State Circuits 55 (1), 38-48, 2019 | 65 | 2019 |
| A 16 Gb/s 3.7 mW/Gb/s 8-tap DFE receiver and baud-rate CDR with 31 kppm tracking bandwidth PA Francese, T Toifl, P Buchmann, M Brändli, C Menolfi, M Kossel, T Morf, ... IEEE Journal of Solid-State Circuits 49 (11), 2490-2502, 2014 | 60 | 2014 |
| 20.3 A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS TM Andersen, F Krismer, JW Kolar, T Toifl, C Menolfi, L Kull, T Morf, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 53 | 2015 |
| 29.1 A 64Gb/s 1.4 pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFET A Cevrero, I Ozkaya, PA Francese, C Menolfi, T Morf, M Brandli, D Kuchta, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 482-483, 2017 | 47 | 2017 |
| Modeling and Pareto optimization of on-chip switched capacitor converters TM Andersen, F Krismer, JW Kolar, T Toifl, C Menolfi, L Kull, T Morf, ... IEEE Transactions on Power Electronics 32 (1), 363-377, 2016 | 47 | 2016 |
| An eight-lane 7-Gb/s/pin source synchronous single-ended RX with equalization and far-end crosstalk cancellation for backplane channels C Aprile, A Cevrero, PA Francese, C Menolfi, M Braendli, M Kossel, T Morf, ... IEEE Journal of Solid-State Circuits 53 (3), 861-872, 2018 | 45 | 2018 |
| A 10 Gb/s 8-tap 6b 2-PAM/4-PAM Tomlinson–Harashima precoding transmitter for future memory-link applications in 22-nm SOI CMOS M Kossel, T Toifl, PA Francese, M Brändli, C Menolfi, P Buchmann, L Kull, ... IEEE Journal of solid-state circuits 48 (12), 3268-3284, 2013 | 44 | 2013 |
