| Recent advances in electrical doping of 2D semiconductor materials: Methods, analyses, and applications H Yoo, K Heo, MHR Ansari, S Cho Nanomaterials 11 (4), 832, 2021 | 72 | 2021 |
| Double-gate junctionless 1T DRAM with physical barriers for retention improvement MHR Ansari, N Navlakha, JY Lee, S Cho IEEE Transactions on Electron Devices 67 (4), 1471-1479, 2020 | 34 | 2020 |
| Doping dependent assessment of accumulation mode and junctionless FET for 1T DRAM MHR Ansari, N Navlakha, JT Lin, A Kranti IEEE Transactions on Electron Devices 65 (3), 1205-1210, 2018 | 32 | 2018 |
| Performance improvement of 1T DRAM by raised source and drain engineering MHR Ansari, S Cho IEEE Transactions on Electron Devices 68 (4), 1577-1584, 2021 | 27 | 2021 |
| 1T-DRAM with shell-doped architecture MHR Ansari, N Navlakha, JT Lin, A Kranti IEEE Transactions on Electron Devices 66 (1), 428-435, 2018 | 25 | 2018 |
| Core-shell dual-gate nanowire charge-trap memory for synaptic operations for neuromorphic applications MHR Ansari, UM Kannan, S Cho Nanomaterials 11 (7), 1773, 2021 | 21 | 2021 |
| Threshold-variation-tolerant coupling-gate α-IGZO synaptic transistor for more reliably controllable hardware neuromorphic system D Kang, JT Jang, S Park, MHR Ansari, JH Bae, SJ Choi, DM Kim, C Kim, ... IEEE Access 9, 59345-59352, 2021 | 20 | 2021 |
| A more hardware-oriented spiking neural network based on leading memory technology and its application with reinforcement learning MH Kim, S Hwang, S Bang, TH Kim, DK Lee, MHR Ansari, S Cho, ... IEEE Transactions on Electron Devices 68 (9), 4411-4417, 2021 | 15 | 2021 |
| Capacitorless 2T-DRAM for higher retention time and sense margin MHR Ansari, J Singh IEEE Transactions on Electron Devices 67 (3), 902-906, 2020 | 15 | 2020 |
| Core-shell dual-gate nanowire memory as a synaptic device for neuromorphic application MHR Ansari, S Cho, JH Lee, BG Park IEEE Journal of the Electron Devices Society 9, 1282-1289, 2021 | 14 | 2021 |
| High Retention With -Oxide- Junctionless Architecture for 1T DRAM MHR Ansari, N Navlakha, JT Lin, A Kranti IEEE Transactions on Electron Devices 65 (7), 2797-2803, 2018 | 13 | 2018 |
| Vertically stacked nanosheet FET: Charge-trapping memory and synapse with linear weight adjustability for neuromorphic computing applications MHR Ansari, H Li, N El-Atab IEEE Transactions on Electron Devices 70 (3), 1344-1350, 2023 | 10 | 2023 |
| Core-shell dual-gate nanowire synaptic transistor with short/long-term plasticity MHR Ansari, D Kim, S Cho, JH Lee, BG Park 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3, 2021 | 6 | 2021 |
| Performance assessment of TFET architectures as 1T-DRAM N Navlakha, MHR Ansari, JT Lin, A Kranti 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018 | 4 | 2018 |
| Ultra Thin Finger-Like Source Region-Based TFET: Temperature Sensor P Singh, A Raman, DS Yadav, N Kumar, A Dixit, MDHR Ansari IEEE Sensors Letters, 2024 | 3 | 2024 |
| Efficient Implementation of Boolean Logic Functions Using Double Gate Charge-Trapping Memory for In-Memory Computing MHR Ansari, N El-Atab IEEE Transactions on Electron Devices, 2024 | 3 | 2024 |
| Reliability improvement of 1T DRAM based on feedback transistor by using local partial insulators D Jang, MHR Ansari, G Kim, S Cho, IH Cho Japanese Journal of Applied Physics 60 (10), 104002, 2021 | 3 | 2021 |
| Nano-scale charge trapping memory based on two-dimensional conjugated microporous polymer A Rezk, MHR Ansari, KC Ranjeesh, S Gaber, D Kumar, A Merhi, ... Scientific Reports 13 (1), 18845, 2023 | 2 | 2023 |
| A Novel Wavy Channel Gate-All-Around FETs for Next-Generation CMOS Applications R Halder, UK Das, MHR Ansari, N El-Atab 2023 IEEE 23rd International Conference on Nanotechnology (NANO), 317-320, 2023 | 2 | 2023 |
| More physical understanding of current characteristics of tunneling field-effect transistor leveraged by gate positions and properties through dual-gate and gate-all-around … MHR Ansari, S Cho, BG Park Applied Physics A 126, 1-8, 2020 | 2 | 2020 |
