팔로우
Shaolin Xie
Shaolin Xie
Alibaba Group Inc.
alibaba-inc.com의 이메일 확인됨 - 홈페이지
제목
인용
인용
연도
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips
S Davidson, S Xie, C Torng, K Al-Hawai, A Rovinski, T Ajayi, L Vega, ...
IEEE Micro 38 (2), 30-41, 2018
1342018
FBNA: A Fully Binarized Neural Network Accelerator
P Guo, H Ma, R Chen, P Li, S Xie, D Wang
2018 28th International Conference on Field Programmable Logic and …, 2018
1022018
Celerity: An Open Source RISC-V Tiered Accelerator Fabric
T Ajayi, K Al-Hawaj, A Amarnath, S Dai, S Davidson, P Gao, G Liu, A Lotfi, ...
Symp. on High Performance Chips (Hot Chips), 2017
382017
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS
A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ...
2019 Symposium on VLSI Circuits, C30-C31, 2019
352019
Fast and Efficient Deep Sparse Multi-Strength Spiking Neural Networks with Dynamic Pruning
R Chen, H Ma, S Xie, P Guo, P Li, D Wang
2018 International Joint Conference on Neural Networks (IJCNN), 1-8, 2018
352018
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix–Matrix Multiplication Accelerator
DH Park, S Pal, S Feng, P Gao, J Tan, A Rovinski, S Xie, C Zhao, ...
IEEE Journal of Solid-State Circuits 55 (4), 933-944, 2020
342020
Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL
A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ...
IEEE Solid-State Circuits Letters 2 (12), 289-292, 2019
332019
Extreme Datacenter Specialization for Planet-Scale Computing: ASIC Clouds
S Xie, S Davidson, I Magaki, M Khazraee, L Vega, L Zhang, MB Taylor
ACM SIGOPS Operating Systems Review 52 (1), 96-108, 2018
332018
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm
S Pal, D Park, S Feng, P Gao, J Tan, A Rovinski, S Xie, C Zhao, ...
2019 Symposium on VLSI Technology, C150-C151, 2019
272019
MaPU: A novel mathematical computing architecture
D Wang, S Xie, X Du, L Yin, C Lin, H Ma, W Ren, H Wang, X Wang, ...
2016 IEEE International Symposium on High Performance Computer Architecture …, 2016
262016
Experiences using the risc-v ecosystem to design an accelerator-centric soc in tsmc 16nm
TAKAH Aporva, ASDS Davidson, PGGLA Rao, ARNSC Torng, LVBVS Xie, ...
1st Workshop on Computer Architecture Research with RISC-V (CARRV 2017), 2017
162017
Low Latency Spiking ConvNets with Restricted Output Training and False Spike Inhibition
R Chen, H Ma, P Guo, S Xie, P Li, D Wang
2018 International Joint Conference on Neural Networks (IJCNN), 1-8, 2018
102018
Parallel Polar Encoding in 5G Communication
Y Guo, S Xie, Z Liu, L Yang, D Wang
2018 IEEE Symposium on Computers and Communications (ISCC), 00064-00069, 2018
62018
The BaseJump Manycore Accelerator Network
S Xie, MB Taylor
arXiv preprint arXiv:1808.00650, 2018
42018
Data access method and device for parallel FFT computation
S Xie, D Wang, X Lin, J Hao, X Xue, T Wang, L Yin
US Patent 9,317,481, 2016
42016
Parallel bit reversal devices and methods
S Xie, D Wang, J Hao, T Wang, L Yin
US Patent 9,268,744, 2016
42016
Parallel bit reversal devices and methods
S Xie, D Wang, J Hao, T Wang, L Yin
US Patent 9,268,744, 2016
42016
Progress in a novel architecture for high performance processing
Z Zhang, M Liu, Z Liu, X Du, S Xie, H Ma, G Ding, W Ren, F Zhou, W Sun, ...
Japanese Journal of Applied Physics 57 (4S), 04FA03, 2018
22018
Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore
DC Jung, M Ruttenberg, P Gao, S Davidson, D Petrisko, K Li, AK Kamath, ...
2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture …, 2024
12024
A reconfigurable ASIC-like image polyphase interpolation implementation method
L Yang, R Guo, S Xie, D Wang
2017 7th IEEE International Conference on Electronics Information and …, 2017
12017
현재 시스템이 작동되지 않습니다. 나중에 다시 시도해 주세요.
학술자료 1–20