| The gem5 simulator: Version 20.0+ J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 342 | 2020 |
| gem5-gpu: A heterogeneous cpu-gpu simulator J Power, J Hestness, M Orr, M Hill, D Wood IEEE, 2014 | 339 | 2014 |
| Heterogeneous system coherence for integrated CPU-GPU systems J Power, A Basu, J Gu, S Puthoor, BM Beckmann, MD Hill, SK Reinhardt, ... Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013 | 216 | 2013 |
| Supporting x86-64 address translation for 100s of GPU lanes J Power, MD Hill, D Wood High Performance Computer Architecture (HPCA), 2014 IEEE 20th International …, 2014 | 197 | 2014 |
| Autotm: Automatic tensor movement in heterogeneous memory systems using integer linear programming M Hildebrand, J Khan, S Trika, J Lowe-Power, V Akella Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | 84 | 2020 |
| Border control: Sandboxing accelerators LE Olson, J Power, MD Hill, DA Wood Proceedings of the 48th International Symposium on Microarchitecture, 470-481, 2015 | 76 | 2015 |
| Performance analysis of scientific computing workloads on general purpose tees A Akram, A Giannakou, V Akella, J Lowe-Power, S Peisert 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2021 | 37 | 2021 |
| Enabling scalable chiplet-based uniform memory architectures with silicon photonics P Fotouhi, S Werner, J Lowe-Power, SJB Yoo Proceedings of the International Symposium on Memory Systems, 222-334, 2019 | 36 | 2019 |
| Filtering translation bandwidth with virtual caching H Yoon, J Lowe-Power, GS Sohi Proceedings of the Twenty-Third International Conference on Architectural …, 2018 | 32 | 2018 |
| Toward GPUs being mainstream in analytic processing: An initial argument using simple scan-aggregate queries J Power, Y Li, MD Hill, JM Patel, DA Wood Proceedings of the 11th International Workshop on Data Management on New …, 2015 | 32 | 2015 |
| Stream floating: Enabling proactive and decentralized cache optimizations Z Wang, J Weng, J Lowe-Power, J Gaur, T Nowatzki 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | 29 | 2021 |
| Enabling reproducible and agile full-system simulation BR Bruce, A Akram, H Nguyen, K Roarty, M Samani, M Friborz, T Reddy, ... 2021 IEEE International Symposium on Performance Analysis of Systems and …, 2021 | 25 | 2021 |
| A case against hardware managed dram caches for nvram based systems M Hildebrand, JT Angeles, J Lowe-Power, V Akella 2021 IEEE International Symposium on Performance Analysis of Systems and …, 2021 | 21 | 2021 |
| The Davis In-Order (DINO) CPU: A Teaching-Focused RISC-V CPU Design J Lowe-Power, C Nitta Proceedings of the Workshop on Computer Architecture Education, 1-8, 2019 | 19 | 2019 |
| Position paper: A case for exposing extra-architectural state in the isa J Lowe-Power, V Akella, MK Farrens, ST King, CJ Nitta Proceedings of the 7th International Workshop on Hardware and Architectural …, 2018 | 19* | 2018 |
| Implications of emerging 3D GPU architecture on the scan primitive J Power, Y Li, MD Hill, JM Patel, DA Wood ACM SIGMOD Record 44 (1), 18-23, 2015 | 16 | 2015 |
| Performance analysis of scientific computing workloads on trusted execution environments A Akram, A Giannakou, V Akella, J Lowe-Power, S Peisert arXiv preprint arXiv:2010.13216, 2020 | 12 | 2020 |
| Enabling design space exploration for risc-v secure compute environments A Akram, V Akella, S Peisert, J Lowe-Power Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021), 2021 | 10 | 2021 |
| Improving provisioned power efficiency in HPC systems with GPU-CAPP K Straube, J Lowe-Power, C Nitta, M Farrens, V Akella 2018 IEEE 25th International Conference on High Performance Computing (HiPC …, 2018 | 10 | 2018 |
| On Heterogeneous Compute and Memory Systems J Lowe-Power The University of Wisconsin-Madison, 2017 | 8 | 2017 |
Venkatesh AkellaProfessor of Electrical & Computer Engineering, University of California, Davisucdavis.edu의 이메일 확인됨