| 29.1 A 40nm 64Kb 56.67 TOPS/W read-disturb-tolerant compute-in-memory/digital RRAM macro with active-feedback-based read and in-situ write verification JH Yoon, M Chang, WS Khwa, YD Chih, MF Chang, A Raychowdhury 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 404-406, 2021 | 90 | 2021 |
| A 40-nm 118.44-TOPS/W voltage-sensing compute-in-memory RRAM macro with write verification and multi-bit encoding JH Yoon, M Chang, WS Khwa, YD Chih, MF Chang, A Raychowdhury IEEE Journal of Solid-State Circuits 57 (3), 845-857, 2022 | 45 | 2022 |
| A 40-nm, 64-kb, 56.67 TOPS/W voltage-sensing computing-in-memory/digital RRAM macro supporting iterative write with verification and online read-disturb detection JH Yoon, M Chang, WS Khwa, YD Chih, MF Chang, A Raychowdhury IEEE Journal of Solid-State Circuits 57 (1), 68-79, 2021 | 42 | 2021 |
| A 0.87 W transceiver IC for 100 gigabit Ethernet in 40 nm CMOS H Won, T Yoon, J Han, JY Lee, JH Yoon, T Kim, JS Lee, S Lee, K Han, ... IEEE Journal of Solid-State Circuits 50 (2), 399-413, 2014 | 35 | 2014 |
| NeuroSLAM: A 65-nm 7.25-to-8.79-TOPS/W mixed-signal oscillator-based SLAM accelerator for edge robotics JH Yoon, A Raychowdhury IEEE Journal of Solid-State Circuits 56 (1), 66-78, 2020 | 34 | 2020 |
| Electronic dispersion compensation for low-cost distributed feedback-directly modulated laser BAE Hyeonmin, K KyeongHa, Y JongHyeok US Patent 9,166,698, 2015 | 20 | 2015 |
| A DC-to-12.5 Gb/s 9.76 mW/Gb/s All-Rate CDR With a SingleLCVCO in 90 nm CMOS JH Yoon, SW Kwon, HM Bae IEEE Journal of Solid-State Circuits 52 (3), 856-866, 2017 | 18 | 2017 |
| A 40nm 100Kb 118.44 TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation JH Yoon, M Chang, WS Khwa, YD Chih, MF Chang, A Raychowdhury 2021 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2021 | 17 | 2021 |
| 32.4 A 1V-Supply -Input-Range 1kHz-BW 181.9dB-FOMDR179.4dB-FOMSNDR 2nd-Order Noise-Shaping SAR-ADC with Enhanced Input Impedance in … G Kim, S Lee, T Seol, S Baik, Y Shin, G Kim, JH Yoon, AK George, J Lee 2023 IEEE International Solid-State Circuits Conference (ISSCC), 484-486, 2023 | 15 | 2023 |
| 31.1 a 65nm 8.79 TOPS/W 23.82 mW mixed-signal oscillator-based NeuroSLAM accelerator for applications in edge robotics JH Yoon, A Raychowdhury 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 478-480, 2020 | 15 | 2020 |
| Bits-net: Bit-sparse deep neural network for energy-efficient rram-based compute-in-memory F Karimzadeh, JH Yoon, A Raychowdhury IEEE Transactions on Circuits and Systems I: Regular Papers 69 (5), 1952-1961, 2022 | 14 | 2022 |
| Improving compute in-memory ecc reliability with successive correction B Crafton, Z Wan, S Spetalnick, JH Yoon, W Wu, C Tokunaga, V De, ... Proceedings of the 59th ACM/IEEE Design Automation Conference, 745-750, 2022 | 13 | 2022 |
| Cim-secded: A 40nm 64kb compute in-memory rram macro with ecc enabling reliable operation B Crafton, S Spetalnick, JH Yoon, W Wu, C Tokunaga, V De, ... 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2021 | 13 | 2021 |
| A 10-Gb/s CDR with an adaptive optimum loop-bandwidth calibrator for serial communication links JY Lee, JH Yoon, HM Bae IEEE Transactions on Circuits and Systems I: Regular Papers 61 (8), 2466-2472, 2014 | 13 | 2014 |
| Adaptive optimum CDR bandwidth estimation by using a kalman gain extractor HM Bae, JY Lee, HS Won, JH Yoon, JH Park, TH Kim US Patent 8,938,043, 2015 | 12 | 2015 |
| A 20Gb/s transceiver with framed-pulsewidth modulation in 40nm CMOS S Jeon, W Kwon, T Yoon, JH Yoon, K Kwon, J Yang, HM Bae 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 270-272, 2018 | 11 | 2018 |
| 3.125-to-28.125 Gb/s 4.72 mW/Gb/s multi-standard parallel transceiver supporting channel-independent operation in 40-nm CMOS JH Yoon, K Kwon, HM Bae IEEE Transactions on Circuits and Systems I: Regular Papers 67 (8), 2647-2658, 2020 | 8 | 2020 |
| A -Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS JY Lee, J Yang, JH Yoon, SW Kwon, H Won, J Han, HM Bae IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (6 …, 2015 | 6 | 2015 |
| Dualpim: A dual-precision and low-power cnn inference engine using sram-and edram-based processing-in-memory arrays S Jung, J Lee, H Noh, JH Yoon, J Kung 2022 IEEE 4th International Conference on Artificial Intelligence Circuits …, 2022 | 5 | 2022 |
| RRAM-ECC: Improving Reliability of RRAM-Based Compute In-Memory Z Wan, B Crafton, S Spetalnick, JH Yoon, A Raychowdhury 13th Annual Non-Volatile Memories Workshop (NVMW), 2022 | 5 | 2022 |
Arijit RaychowdhurySteve W. Chaddick School Chair for ECE, Georgia Institute of Technologyece.gatech.edu의 이메일 확인됨