| 15.3 A 351TOPS/W and 372.4 GOPS compute-in-memory SRAM macro in 7nm FinFET CMOS for machine-learning applications Q Dong, ME Sinangil, B Erbagci, D Sun, WS Khwa, HJ Liao, Y Wang, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 242-244, 2020 | 312 | 2020 |
| A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS/W fully parallel product-sum operation for binary DNN edge processors WS Khwa, JJ Chen, JF Li, X Si, EY Yang, X Sun, R Liu, PY Chen, Q Li, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 496-498, 2018 | 274 | 2018 |
| 16.1 A 22nm 4Mb 8b-precision ReRAM computing-in-memory macro with 11.91 to 195.7 TOPS/W for tiny AI edge devices CX Xue, JM Hung, HY Kao, YH Huang, SP Huang, FC Chang, P Chen, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 245-247, 2021 | 177 | 2021 |
| A dual-split 6T SRAM-based computing-in-memory unit-macro with fully parallel product-sum operation for binarized DNN edge processors X Si, WS Khwa, JJ Chen, JF Li, X Sun, R Liu, S Yu, H Yamauchi, Q Li, ... IEEE Transactions on Circuits and Systems I: Regular Papers 66 (11), 4172-4185, 2019 | 150 | 2019 |
| A 7-nm compute-in-memory SRAM macro supporting multi-bit input, weight and output and achieving 351 TOPS/W and 372.4 GOPS ME Sinangil, B Erbagci, R Naous, K Akarvardar, D Sun, WS Khwa, ... IEEE Journal of Solid-State Circuits 56 (1), 188-198, 2020 | 143 | 2020 |
| Parallelizing SRAM arrays with customized bit-cell for binary neural networks R Liu, X Peng, X Sun, WS Khwa, X Si, JJ Chen, JF Li, MF Chang, S Yu Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 127 | 2018 |
| A 5.1 pJ/neuron 127.3 us/inference RNN-based speech recognition processor using 16 computing-in-memory SRAM macros in 65nm CMOS R Guo, Y Liu, S Zheng, SY Wu, P Ouyang, WS Khwa, X Chen, JJ Chen, ... 2019 Symposium on VLSI Circuits, C120-C121, 2019 | 113 | 2019 |
| Length-adjustable ossicular prosthesis J Roberson, J Shadduck US Patent App. 10/262,725, 2003 | 100 | 2003 |
| An 8-Mb DC-current-free binary-to-8b precision ReRAM nonvolatile computing-in-memory macro using time-space-readout with 1286.4-21.6 TOPS/W for edge-AI devices JM Hung, YH Huang, SP Huang, FC Chang, TH Wen, CI Su, WS Khwa, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 92 | 2022 |
| 29.1 A 40nm 64Kb 56.67 TOPS/W read-disturb-tolerant compute-in-memory/digital RRAM macro with active-feedback-based read and in-situ write verification JH Yoon, M Chang, WS Khwa, YD Chih, MF Chang, A Raychowdhury 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 404-406, 2021 | 90 | 2021 |
| A 40-nm, 2M-cell, 8b-precision, hybrid SLC-MLC PCM computing-in-memory macro with 20.5-65.0 TOPS/W for tiny-Al edge devices WS Khwa, YC Chiu, CJ Jhang, SP Huang, CY Lee, TH Wen, FC Chang, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 89 | 2022 |
| A four-megabit compute-in-memory macro with eight-bit precision based on CMOS and resistive random-access memory for AI edge devices JM Hung, CX Xue, HY Kao, YH Huang, FC Chang, SP Huang, TW Liu, ... Nature Electronics 4 (12), 921-930, 2021 | 84 | 2021 |
| A 22nm 4Mb STT-MRAM data-encrypted near-memory computation macro with a 192GB/s read-and-decryption bandwidth and 25.1-55.1 TOPS/W 8b MAC for AI operations YC Chiu, CS Yang, SH Teng, HY Huang, FC Chang, Y Wu, YA Chien, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 178-180, 2022 | 66 | 2022 |
| CHIMERA: A 0.92 TOPS, 2.2 TOPS/W edge AI accelerator with 2 MByte on-chip foundry resistive RAM for efficient training and inference M Giordano, K Prabhu, K Koul, RM Radway, A Gural, R Doshi, ZF Khan, ... 2021 symposium on VLSI circuits, 1-2, 2021 | 63 | 2021 |
| Design of nonvolatile SRAM with ferroelectric FETs for energy-efficient backup and restore X Li, K Ma, S George, WS Khwa, J Sampson, S Gupta, Y Liu, MF Chang, ... IEEE Transactions on Electron Devices 64 (7), 3037-3040, 2017 | 60 | 2017 |
| Cold CMOS as a power-performance-reliability booster for advanced FinFETs HL Chiang, TC Chen, JF Wang, S Mukhopadhyay, WK Lee, CL Chen, ... 2020 IEEE Symposium on VLSI Technology, 1-2, 2020 | 59 | 2020 |
| SAPIENS: A 64-kb RRAM-based non-volatile associative memory for one-shot learning and inference at the edge H Li, WC Chen, A Levy, CH Wang, H Wang, PH Chen, W Wan, WS Khwa, ... IEEE Transactions on Electron Devices 68 (12), 6637-6643, 2021 | 58 | 2021 |
| A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range SD Spetalnick, M Chang, B Crafton, WS Khwa, YD Chih, MF Chang, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 57 | 2022 |
| A 40nm low-power logic compatible phase change memory technology JY Wu, YS Chen, WS Khwa, SM Yu, TY Wang, JC Tseng, YD Chih, ... 2018 IEEE International Electron Devices Meeting (IEDM), 27.6. 1-27.6. 4, 2018 | 54 | 2018 |
| A 40nm 60.64 TOPS/W ECC-capable compute-in-memory/digital 2.25 MB/768KB RRAM/SRAM system with embedded cortex M3 microprocessor for edge recommendation systems M Chang, SD Spetalnick, B Crafton, WS Khwa, YD Chih, MF Chang, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 50 | 2022 |