| Complementary Dual Codes for Counter-Measures to Side-Channel Attacks. C Carlet, S Guilley ICMCTA, 97-105, 2014 | 405 | 2014 |
| RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs M Nassar, Y Souissi, S Guilley, JL Danger 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012 | 219 | 2012 |
| Practical setup time violation attacks on AES N Selmane, S Guilley, JL Danger 2008 Seventh European Dependable Computing Conference, 91-96, 2008 | 213 | 2008 |
| Hardware Trojan horses in cryptographic IP cores S Bhasin, JL Danger, S Guilley, XT Ngo, L Sauvage 2013 Workshop on Fault Diagnosis and Tolerance in Cryptography, 15-29, 2013 | 173 | 2013 |
| Orthogonal direct sum masking: A smartcard friendly computation paradigm in a code, with builtin protection against side-channel and fault attacks J Bringer, C Carlet, H Chabanne, S Guilley, H Maghrebi IFIP International Workshop on Information Security Theory and Practice, 40-56, 2014 | 155 | 2014 |
| Good is not good enough: Deriving optimal distinguishers from communication theory A Heuser, O Rioul, S Guilley Cryptographic Hardware and Embedded Systems–CHES 2014: 16th International …, 2014 | 152 | 2014 |
| Differential power analysis model and some results S Guilley, P Hoogvorst, R Pacalet Smart Card Research and Advanced Applications VI: IFIP 18th World Computer …, 2004 | 151 | 2004 |
| Side-channel analysis and machine learning: A practical perspective S Picek, A Heuser, A Jovic, SA Ludwig, S Guilley, D Jakobovic, ... 2017 International Joint Conference on Neural Networks (IJCNN), 4095-4102, 2017 | 148 | 2017 |
| High speed true random number generator based on open loop structures in FPGAs JL Danger, S Guilley, P Hoogvorst Microelectronics journal 40 (11), 1650-1656, 2009 | 136 | 2009 |
| NICV: normalized inter-class variance for detection of side-channel leakage S Bhasin, JL Danger, S Guilley, Z Najm 2014 International Symposium on Electromagnetic Compatibility, Tokyo, 310-313, 2014 | 117 | 2014 |
| Best information is most successful E De Chérisey, S Guilley, O Rioul, P Piantanida Cryptology ePrint Archive, 2019 | 115 | 2019 |
| BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation M Nassar, S Bhasin, JL Danger, G Duc, S Guilley 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 115 | 2010 |
| Linear complementary dual code improvement to strengthen encoded circuit against hardware Trojan horses XT Ngo, S Bhasin, JL Danger, S Guilley, Z Najm 2015 IEEE International Symposium on Hardware Oriented Security and Trust …, 2015 | 105 | 2015 |
| An easy-to-design PUF based on a single oscillator: The loop PUF Z Cherif, JL Danger, S Guilley, L Bossuet 2012 15th Euromicro Conference on Digital System Design, 156-162, 2012 | 103 | 2012 |
| The “Backend Duplication” Method: A Leakage-Proof Place-and-Route Strategy for ASICs S Guilley, P Hoogvorst, Y Mathieu, R Pacalet Cryptographic Hardware and Embedded Systems–CHES 2005: 7th International …, 2005 | 86 | 2005 |
| WDDL is protected against setup time violation attacks N Selmane, S Bhasin, S Guilley, T Graba, JL Danger 2009 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), 73-83, 2009 | 84 | 2009 |
| Template attack versus Bayes classifier S Picek, A Heuser, S Guilley Journal of Cryptographic Engineering 7 (4), 343-351, 2017 | 82 | 2017 |
| Electromagnetic radiations of fpgas: High spatial resolution cartography and attack on a cryptographic module L Sauvage, S Guilley, Y Mathieu ACM Transactions on Reconfigurable Technology and Systems (TRETS) 2 (1), 1-24, 2009 | 81 | 2009 |
| CMOS structures suitable for secured hardware S Guilley, P Hoogvorst, Y Mathieu, R Pacalet, J Provost Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004 | 81 | 2004 |
| Overview of dual rail with precharge logic styles to thwart implementation-level attacks on hardware cryptoprocessors JL Danger, S Guilley, S Bhasin, M Nassar 2009 3rd International Conference on Signals, Circuits and Systems (SCS), 1-8, 2009 | 79 | 2009 |
Jean-Luc DangerLTCI, Télécom Paris, Institut Polytechnique de Parisenst.fr의 이메일 확인됨