| Processor hardware security vulnerabilities and their detection by unique program execution checking MR Fadiheh, D Stoffel, C Barrett, S Mitra, W Kunz 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 994-999, 2019 | 70 | 2019 |
| A formal approach for detecting vulnerabilities to transient execution attacks in out-of-order processors MR Fadiheh, J Müller, R Brinkmann, S Mitra, D Stoffel, W Kunz 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 52 | 2020 |
| Symbolic quick error detection using symbolic initial state for pre-silicon verification MR Fadiheh, J Urdahl, SS Nuthakki, S Mitra, C Barrett, D Stoffel, W Kunz 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 55-60, 2018 | 27 | 2018 |
| An exhaustive approach to detecting transient execution side channels in RTL designs of processors MR Fadiheh, A Wezel, J Müller, J Bormann, S Ray, JM Fung, S Mitra, ... IEEE Transactions on Computers 72 (1), 222-235, 2022 | 26 | 2022 |
| Gap-free Processor Verification by S2QED and Property Generation K Devarajegowda, MR Fadiheh, E Singh, C Barrett, S Mitra, W Ecker, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 526-531, 2020 | 26 | 2020 |
| Sayak Ray, Jason M. Fung, Subhasish Mitra, Dominik Stoffel, and Wolfgang Kunz. An exhaustive approach to detecting transient execution side channels in RTL designs of processors MR Fadiheh, A Wezel, J Müller, J Bormann IEEE Transactions on Computers 72 (1), 222-235, 2023 | 19 | 2023 |
| A formal approach to confidentiality verification in SoCs at the register transfer level J Müller, MR Fadiheh, ALD Antón, T Eisenbarth, D Stoffel, W Kunz 2021 58th ACM/IEEE Design Automation Conference (DAC), 991-996, 2021 | 18 | 2021 |
| Symbolic qed pre-silicon verification for automotive microcontroller cores: Industrial case study E Singh, K Devarajegowda, S Simon, R Schnieder, K Ganesan, ... 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019 | 15 | 2019 |
| Towards a formally verified hardware root-of-trust for data-oblivious computing L Deutschmann, J Müller, MR Fadiheh, D Stoffel, W Kunz Proceedings of the 59th ACM/IEEE Design Automation Conference, 727-732, 2022 | 12 | 2022 |
| Fault attacks on access control in processors: Threat, formal analysis and microarchitectural mitigation ALD Antón, J Müller, MR Fadiheh, D Stoffel, W Kunz IEEE Access 11, 52695-52711, 2023 | 10 | 2023 |
| A scalable formal verification methodology for data-oblivious hardware L Deutschmann, J Müller, MR Fadiheh, D Stoffel, W Kunz IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | 7 | 2024 |
| Design of Access Control Mechanisms in {Systems-on-Chip} with Formal Integrity Guarantees D Mehmedagić, MR Fadiheh, J Müller, ALD Antón, D Stoffel, W Kunz 32nd USENIX Security Symposium (USENIX Security 23), 2779-2796, 2023 | 6 | 2023 |
| Effective pre-silicon verification of processor cores by breaking the bounds of symbolic quick error detection K Ganesan, F Lonsing, SS Nuthakki, E Singh, MR Fadiheh, W Kunz, ... arXiv preprint arXiv:2106.10392, 2021 | 5 | 2021 |
| Secure-by-construction design methodology for CPUs: Implementing secure speculation on the RTL T Jauch, A Wezel, MR Fadiheh, P Schmitz, S Ray, JM Fung, CW Fletcher, ... 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 1-9, 2023 | 3 | 2023 |
| A Golden-Free Formal Method for Trojan Detection in Non-Interfering Accelerators ALD Antón, J Müller, L Deutschmann, MR Fadiheh, D Stoffel, W Kunz 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2024 | 2 | 2024 |
| VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL ALD Antón, J Müller, P Schmitz, T Jauch, A Wezel, L Deutschmann, ... arXiv preprint arXiv:2407.18679, 2024 | 1 | 2024 |
| Unique Program Execution Checking: A Novel Approach for Formal Security Analysis of Hardware. MR Fadiheh Kaiserslautern University of Technology, Germany, 2022 | 1 | 2022 |
| Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking M Rahmani Fadiheh, D Stoffel, C Barrett, S Mitra, W Kunz arXiv e-prints, arXiv: 1812.04975, 2018 | 1 | 2018 |
| QED and Symbolic QED: Dramatic Improvements in Pre-Silicon Verification and Post-Silicon Validation K Devarajegowda, F Lonsing, MR Fadiheh, S Chattopadhyay, D Lin, ... Foundations and Trends® in Integrated Circuits and Systems 3 (2–3), 51-217, 2024 | | 2024 |
| VeriCHERI: Exhaustive Formal Security Verification of CHERI at the RTL AL Duque Antón, J Müller, P Schmitz, T Jauch, A Wezel, L Deutschmann, ... arXiv e-prints, arXiv: 2407.18679, 2024 | | 2024 |