| Pact: Parameterized clipping activation for quantized neural networks J Choi, Z Wang, S Venkataramani, PIJ Chuang, V Srinivasan, ... arXiv preprint arXiv:1805.06085, 2018 | 1142 | 2018 |
| Training deep neural networks with 8-bit floating point numbers N Wang, J Choi, D Brand, CY Chen, K Gopalakrishnan Advances in neural information processing systems 31, 2018 | 643 | 2018 |
| Hybrid 8-bit floating point (HFP8) training and inference for deep neural networks X Sun, J Choi, CY Chen, N Wang, S Venkataramani, VV Srinivasan, X Cui, ... Advances in neural information processing systems 32, 2019 | 263 | 2019 |
| Accurate and Efficient 2-bit Quantized Neural Networks J Choi, S Venkataramani, V Srinivasan, K Gopalakrishnan, Z Wang, ... The Conference on Systems and Machine Learning (SysML), 2019 | 212 | 2019 |
| Adacomp: Adaptive residual gradient compression for data-parallel distributed training CY Chen, J Choi, D Brand, A Agrawal, W Zhang, K Gopalakrishnan Proceedings of the AAAI conference on artificial intelligence 32 (1), 2018 | 211 | 2018 |
| A scalable multi-TeraOPS deep learning processor core for AI trainina and inference B Fleischer, S Shukla, M Ziegler, J Silberman, J Oh, V Srinivasan, J Choi, ... 2018 IEEE symposium on VLSI circuits, 35-36, 2018 | 154 | 2018 |
| Robust machine learning systems: Challenges, current trends, perspectives, and the road ahead M Shafique, M Naseer, T Theocharides, C Kyrkou, O Mutlu, L Orosa, ... IEEE Design & Test 37 (2), 30-57, 2020 | 153 | 2020 |
| Approximate computing: Challenges and opportunities A Agrawal, J Choi, K Gopalakrishnan, S Gupta, R Nair, J Oh, DA Prener, ... 2016 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2016 | 126 | 2016 |
| DLFloat: A 16-bit Floating Point Format Designed for Deep Learning Training and Inference A Agrawal, SM Mueller, BM Fleischer, J Choi, N Wang, X Sun, ... 26th IEEE Symposium on Computer Arithmetic, 2019 | 103 | 2019 |
| RaPiD: AI accelerator for ultra-low precision training and inference S Venkataramani, V Srinivasan, W Wang, S Sen, J Zhang, A Agrawal, ... 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 96 | 2021 |
| 9.1 A 7nm 4-core AI chip with 25.6 TFLOPS hybrid FP8 training, 102.4 TOPS INT4 inference and workload-aware throttling A Agrawal, SK Lee, J Silberman, M Ziegler, M Kang, S Venkataramani, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 144-146, 2021 | 89 | 2021 |
| Bridging the accuracy gap for 2-bit quantized neural networks (qnn) J Choi, PIJ Chuang, Z Wang, S Venkataramani, V Srinivasan, ... arXiv preprint arXiv:1807.06964, 2018 | 89 | 2018 |
| Compensated-DNN: Energy efficient low-precision deep neural networks by compensating quantization errors S Jain, S Venkataramani, V Srinivasan, J Choi, P Chuang, L Chang Proceedings of the 55th annual design automation conference, 1-6, 2018 | 80 | 2018 |
| Exploiting approximate computing for deep learning acceleration CY Chen, J Choi, K Gopalakrishnan, V Srinivasan, S Venkataramani 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 821-826, 2018 | 80 | 2018 |
| PROMISE: An end-to-end design of a programmable mixed-signal accelerator for machine-learning algorithms P Srivastava, M Kang, SK Gonugondla, S Lim, J Choi, V Adve, NS Kim, ... 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 72 | 2018 |
| Efficient AI system design with cross-layer approximate computing S Venkataramani, X Sun, N Wang, CY Chen, J Choi, M Kang, A Agarwal, ... Proceedings of the IEEE 108 (12), 2232-2250, 2020 | 61 | 2020 |
| Understanding the role of self attention for efficient speech recognition K Shim, J Choi, W Sung International Conference on Learning Representations, 2021 | 56 | 2021 |
| OPTIMUS: OPTImized matrix MUltiplication Structure for Transformer neural network accelerator J Park, H Yoon, D Ahn, J Choi, JJ Kim Third Conference on Machine Learning and Systems, 2020 | 53 | 2020 |
| Biscaled-dnn: Quantizing long-tailed datastructures with two scale factors for deep neural networks S Jain, S Venkataramani, V Srinivasan, J Choi, K Gopalakrishnan, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 50 | 2019 |
| A real-time FPGA-based 20 000-word speech recognizer with optimized DRAM access YK Choi, K You, J Choi, W Sung IEEE Transactions on Circuits and Systems I: Regular Papers 57 (8), 2119-2131, 2010 | 49 | 2010 |
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