Reiner Hartenstein

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Reiner Hartenstein

University of Kaiserslautern & KIT Karlsruhe

Patvirtintas el. paštas hartenstein.de - Pagrindinis puslapis

FPGA Xputer Reconfigurable Computing Power-efficient Computing Computer Architecture


Pavadinimas Rūšiuoti pagal šaltinius Rūšiuoti pagal metus Rūšiuoti pagal pavadinimą	Cituota Cituota	Metai
A decade of reconfigurable computing: a visionary retrospective R Hartenstein Proceedings design, automation and test in Europe. Conference and exhibition …, 2001	995	2001
Introduction to reconfigurable computing: architectures, algorithms, and applications C Bobda, R Hartenstein Springer 1 (1.5), 2007	363	2007
Coarse grain reconfigurable architecture (embedded tutorial) R Hartenstein Proceedings of the 2001 Asia and South Pacific Design Automation Conference …, 2001	320	2001
Seeking solutions in configurable computing WH Mangione-Smith, B Hutchings, D Andrews, A DeHon, C Ebeling, ... Computer 30 (12), 38-43, 1997	257	1997
A datapath synthesis system for the reconfigurable datapath architecture RW Hartenstein, R Kress Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair, 479-484, 1995	205	1995
KressArray Xplorer: a new CAD environment to optimize Reconfigurable Datapath Array R Hartenstein, M Herz, T Hoffmann, U Nageldinger Proceedings of the 2000 Asia and South Pacific Design Automation Conference …, 2000	137	2000
A new FPGA architecture for word-oriented datapaths RW Hartenstein, R Kress, H Reinig Field-Programmable Logic Architectures, Synthesis and Applications: 4th …, 1994	115	1994
Parallelization in co-compilation for configurable accelerators-a host/accelerator partitioning compilation method J Becker, R Hartenstein, M Herz, U Nageldinger Proceedings of 1998 Asia and South Pacific Design Automation Conference, 23-33, 1998	109	1998
Configware and morphware going mainstream J Becker, R Hartenstein Journal of Systems Architecture 49 (4-6), 127-142, 2003	106	2003
A novel ASIC design approach based on a new machine paradigm RW Hartenstein, AG Hirschbiel, M Riedmuller, K Schmidt, M Weber IEEE Journal of Solid-State Circuits 26 (7), 975-989, 1991	89	1991
Learning spatiotemporal T-junctions for occlusion detection N Apostoloff, A Fitzgibbon 2005 IEEE Computer Society Conference on Computer Vision and Pattern …, 2005	81	2005
Using the KressArray for reconfigurable computing R Hartenstein, M Herz, T Hoffmann, U Nageldinger Proc. SPIE 3526, 150-161, 1998	69	1998
Trends in reconfigurable logic and reconfigurable computing R Hartenstein 9th International Conference on Electronics, Circuits and Systems 2, 801-808, 2002	66	2002
Fundamentals of structured hardware design: a design language approach at register transfer level R Hartenstein (No Title), 1977	63	1977
Reconfigurable systems for sequence alignment and for general dynamic programming RP Jacobi, M Ayala-Rincón, LGA Carvalho, CH Llanos, RW Hartenstein Genetics and Molecular Research 4 (3), 543-552, 2005	57	2005
A novel paradigm of parallel computation and its use to implement simple high performance hardware RW Hartenstein, AG Hirschbiel, M Weber International Conference on Vector and Parallel Processing, 51-62, 1990	57	1990
A reconfigurable data-driven ALU for Xputers RW Hartenstein, R Kress, H Reinig Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines, 139-146, 1994	56	1994
A general approach in system design integrating reconfigurable accelerators RW Hartenstein, J Becker, M Herz, U Nageldinger 1996 Proceedings. Eighth Annual IEEE International Conference on Innovative …, 1996	52	1996
Reconfigurable computing: A new business model-and its impact on SoC design R Hartenstein Proceedings Euromicro Symposium on Digital Systems Design, 103-110, 2001	51	2001
On reconfgurable co-processing units RW Hartenstein, M Herz, T Hoffmann, U Nageldinger Parallel and Distributed Processing: 10 IPPS/SPDP'98 Workshops Held in …, 1998	51	1998

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