Razor: A low-power pipeline based on circuit-level timing speculation D Ernst, NS Kim, S Das, S Pant, R Rao, T Pham, C Ziesler, D Blaauw, ... Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003 | 1806 | 2003 |
Leakage current: Moore's law meets static power NS Kim, T Austin, D Baauw, T Mudge, K Flautner, JS Hu, MJ Irwin, ... computer 36 (12), 68-75, 2003 | 1804 | 2003 |
Drowsy caches: simple techniques for reducing leakage power K Flautner, NS Kim, S Martin, D Blaauw, T Mudge ACM SIGARCH Computer architecture news 30 (2), 148-157, 2002 | 1231 | 2002 |
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads SM Martin, K Flautner, T Mudge, D Blaauw Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002 | 680 | 2002 |
A self-tuning DVS processor using delay-error detection and correction S Das, D Roberts, S Lee, S Pant, D Blaauw, T Austin, K Flautner, T Mudge IEEE Journal of Solid-State Circuits 41 (4), 792-804, 2006 | 588 | 2006 |
Theoretical and practical limits of dynamic voltage scaling B Zhai, D Blaauw, D Sylvester, K Flautner Proceedings of the 41st Annual Design Automation Conference, 868-873, 2004 | 565 | 2004 |
Razor: circuit-level correction of timing errors for low-power operation D Ernst, S Das, S Lee, D Blaauw, T Austin, T Mudge, NS Kim, K Flautner IEEE Micro 24 (6), 10-20, 2004 | 559 | 2004 |
Automatic performance setting for dynamic voltage scaling K Flautner, S Reinhardt, T Mudge Proceedings of the 7th annual international conference on Mobile computing …, 2001 | 391 | 2001 |
SODA: A low-power architecture for software radio Y Lin, H Lee, M Woh, Y Harel, S Mahlke, T Mudge, C Chakrabarti, ... ACM SIGARCH Computer Architecture News 34 (2), 89-101, 2006 | 331 | 2006 |
A power-efficient 32 bit ARM processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation D Bull, S Das, K Shivashankar, GS Dasika, K Flautner, D Blaauw IEEE Journal of Solid-State Circuits 46 (1), 18-31, 2010 | 274* | 2010 |
PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor T Kgil, S D'Souza, A Saidi, N Binkert, R Dreslinski, T Mudge, S Reinhardt, ... Proceedings of the 12th international conference on Architectural support …, 2006 | 271 | 2006 |
Circuit and microarchitectural techniques for reducing cache leakage power NS Kim, K Flautner, D Blaauw, T Mudge IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (2), 167-184, 2004 | 270 | 2004 |
Vertigo: Automatic performance-setting for linux K Flautner, T Mudge ACM SIGOPS Operating Systems Review 36 (SI), 105-116, 2002 | 254 | 2002 |
Application-specific processing on a general-purpose core via transparent instruction set customization N Clark, M Kudlur, H Park, S Mahlke, K Flautner 37th international symposium on microarchitecture (MICRO-37'04), 30-40, 2004 | 253 | 2004 |
Drowsy instruction caches. leakage power reduction using dynamic voltage scaling and cache sub-bank prediction NS Kim, K Flautner, D Blaauw, T Mudge 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002 …, 2002 | 250 | 2002 |
Making typical silicon matter with razor T Austin, D Blaauw, T Mudge, K Flautner Computer 37 (3), 57-65, 2004 | 218 | 2004 |
An architecture framework for transparent instruction set customization in embedded processors N Clark, J Blome, M Chu, S Mahlke, S Biles, K Flautner 32nd International Symposium on Computer Architecture (ISCA'05), 272-283, 2005 | 214 | 2005 |
Evolution of thread-level parallelism in desktop applications G Blake, RG Dreslinski, T Mudge, K Flautner Proceedings of the 37th annual international symposium on Computer …, 2010 | 147 | 2010 |
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling B Zhai, D Blaauw, D Sylvester, K Flautner IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (11 …, 2005 | 144 | 2005 |
Performance control within a multi-processor system K Flautner US Patent 7,134,031, 2006 | 133 | 2006 |