Volgen
Nagarajan Ranganathan
Nagarajan Ranganathan
Distinguished University Professor Emeritus of Computer Science, University of South Florida
Geverifieerd e-mailadres voor cse.usf.edu - Homepage
Titel
Geciteerd door
Geciteerd door
Jaar
Gabor filter-based edge detection
R Mehrotra, KR Namuduri, N Ranganathan
Pattern recognition 25 (12), 1479-1494, 1992
5871992
LECTOR: a technique for leakage reduction in CMOS circuits
N Hanchate, N Ranganathan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (2), 196-205, 2004
3032004
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs
H Thapliyal, N Ranganathan
ACM Journal on Emerging Technologies in Computing Systems (JETC) 6 (4), 1-31, 2010
2802010
Reversible logic-based concurrently testable latches for molecular QCA
H Thapliyal, N Ranganathan
IEEE transactions on nanotechnology 9 (1), 62-69, 2009
2162009
Design of efficient reversible binary subtractors based on a new reversible gate
H Thapliyal, N Ranganathan
2009 IEEE computer society annual symposium on VLSI, 229-234, 2009
2002009
Corner detection
R Mehrotra, S Nichani, N Ranganathan
Pattern recognition 23 (11), 1223-1233, 1990
1991990
Design of testable reversible sequential circuits
H Thapliyal, N Ranganathan, S Kotiyal
IEEE transactions on very large scale integration (VLSI) systems 21 (7 …, 2012
1962012
JAGUAR: A fully pipelined VLSI architecture for JPEG image compression standard
M Kovac, N Ranganathan
Proceedings of the IEEE 83 (2), 247-258, 1995
1811995
Design of efficient reversible logic-based binary and BCD adder circuits
H Thapliyal, N Ranganathan
ACM Journal on Emerging Technologies in Computing Systems (JETC) 9 (3), 1-31, 2013
1472013
Design of a reversible ALU based on novel programmable reversible logic gate structures
M Morrison, N Ranganathan
2011 IEEE computer society annual symposium on VLSI, 126-131, 2011
1452011
Development of through silicon via (TSV) interposer technology for large die (21× 21mm) fine-pitch Cu/low-k FCBGA package
X Zhang, TC Chai, JH Lau, CS Selvanayagam, K Biswas, S Liu, D Pinjala, ...
2009 59th Electronic components and technology conference, 305-312, 2009
1362009
Low-power high-level synthesis for nanoscale CMOS circuits
SP Mohanty, N Ranganathan, E Kougianos, P Patra
Springer Science & Business Media, 2008
1242008
High-speed VLSI designs for Lempel-Ziv-based data compression
N Ranganathan, S Henriques
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1993
1231993
Influence of Bosch etch process on electrical isolation of TSV structures
N Ranganathan, DY Lee, L Youhe, GQ Lo, K Prasad, KL Pey
IEEE Transactions on components, packaging and manufacturing technology 1 …, 2011
1172011
Improving accuracy in Mitchell's logarithmic multiplication using operand decomposition
V Mahalingam, N Ranganathan
IEEE Transactions on Computers 55 (12), 1523-1535, 2006
1162006
Design of reversible latches optimized for quantum cost, delay and garbage outputs
H Thapliyal, N Ranganathan
2010 23rd international conference on VLSI design, 235-240, 2010
1052010
VLSI implementation of invisible digital watermarking algorithms towards the development of a secure JPEG encoder
SP Mohanty, N Ranganathan, RK Namballa
2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No. 03TH8682 …, 2003
1022003
Efficient VLSI designs for data transformation of tree-based codes
A Mukherjee, N Ranganathan, M Bassiouni
IEEE transactions on circuits and systems 38 (3), 306-314, 2002
1022002
Mach-Zehnder interferometer based design of all optical reversible binary adder
S Kotiyal, H Thapliyal, N Ranganathan
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 721-726, 2012
1012012
Design of a comparator tree based on reversible logic
H Thapliyal, N Ranganathan, R Ferreira
10th IEEE International Conference on Nanotechnology, 1113-1116, 2010
982010
Het systeem kan de bewerking nu niet uitvoeren. Probeer het later opnieuw.
Artikelen 1–20