Siddharth Garg

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Ramesh Karri కర్రి రమేష్Professor of Electrical and Computer Engineering, New York UniversityGeverifieerd e-mailadres voor nyu.edu
Diana MarculescuThe University of Texas at AustinGeverifieerd e-mailadres voor utexas.edu
Jeff J. ZHANGArizona State UniversityGeverifieerd e-mailadres voor seas.harvard.edu
Muhammad ShafiqueProfessor, ECE, New York University (AD-UAE, Tandon-USA), Director eBRAIN LabGeverifieerd e-mailadres voor nyu.edu
Mahesh TripunitaraProfessor, University of WaterlooGeverifieerd e-mailadres voor uwaterloo.ca
Elza ErkipNew York UniversityGeverifieerd e-mailadres voor nyu.edu
Jörg HenkelProfessor of Computer Science, Karlsruhe Institute of TechnologyGeverifieerd e-mailadres voor kit.edu
Yatish TurakhiaAssistant Professor, University of California, San DiegoGeverifieerd e-mailadres voor ucsd.edu
Jeyavijayan (JV) RajendranAssociate Professor of Electrical and Computer Engineering, Texas A&M UniversityGeverifieerd e-mailadres voor tamu.edu
Da-Cheng JuanGoogle Research, National Tsing Hua University, Carnegie Mellon UniversityGeverifieerd e-mailadres voor dacheng.info
Frank ImesonPhd Graduate, University of WaterlooGeverifieerd e-mailadres voor uwaterloo.ca
Radu MarculescuThe University of Texas at AustinGeverifieerd e-mailadres voor utexas.edu
Umit Yusuf OgrasGene Amdahl Professor, University of Wisconsin-MadisonGeverifieerd e-mailadres voor wisc.edu
Shreyas SundaramMarie Gordon Professor of Electrical and Computer Engineering, Purdue UniversityGeverifieerd e-mailadres voor purdue.edu
Catherine RosenbergUniversity of WaterlooGeverifieerd e-mailadres voor ece.uwaterloo.ca
Dariush FooladivandaPostdoctoral Fellow, UC BerkeleyGeverifieerd e-mailadres voor berkeley.edu
Ashish R. HotaAssistant Professor, Indian Institute of Technology (IIT), KharagpurGeverifieerd e-mailadres voor ee.iitkgp.ac.in
Chirag RavishankarSoftware Engineer, AMDGeverifieerd e-mailadres voor xilinx.com
Tulika MitraProfessor of Computer Science, National University of SingaporeGeverifieerd e-mailadres voor comp.nus.edu.sg
Farinaz KoushanfarProfessor and Siavouche Nemat-Nasser Endowed Chair of ECE, UC San DiegoGeverifieerd e-mailadres voor ucsd.edu

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Siddharth Garg

Institute Associate Professor, New York University

Geverifieerd e-mailadres voor nyu.edu - Homepage

AI/ML Hardware Security Privacy


Titel Sorteren op citaties Sorteren op jaar Sorteren op titel	Geciteerd door Geciteerd door	Jaar
Badnets: Identifying vulnerabilities in the machine learning model supply chain T Gu, B Dolan-Gavitt, S Garg arXiv preprint arXiv:1708.06733, 2017	2014	2017
Fine-pruning: Defending against backdooring attacks on deep neural networks K Liu, B Dolan-Gavitt, S Garg International Symposium on Research in Attacks, Intrusions, and Defenses …, 2018	1258	2018
Badnets: Evaluating backdooring attacks on deep neural networks T Gu, K Liu, B Dolan-Gavitt, S Garg IEEE Access 7, 47230-47244, 2019	1233	2019
Securing computer hardware using 3d integrated circuit ({IC}) technology and split manufacturing for obfuscation F Imeson, A Emtenan, S Garg, M Tripunitara 22nd {USENIX} Security Symposium ({USENIX} Security 13), 495-510, 2013	262	2013
Integrated circuit (IC) decamouflaging: Reverse engineering camouflaged ICs within minutes. M El Massad, S Garg, MV Tripunitara NDSS, 1-14, 2015	243	2015
The EDA challenges in the dark silicon era: Temperature, reliability, and variability perspectives M Shafique, S Garg, J Henkel, D Marculescu Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014	242	2014
Safetynets: Verifiable execution of deep neural networks on an untrusted cloud Z Ghodsi, T Gu, S Garg Advances in Neural Information Processing Systems 30, 2017	221	2017
Benchmarking large language models for automated verilog rtl code generation S Thakur, B Ahmad, Z Fan, H Pearce, B Tan, R Karri, B Dolan-Gavitt, ... 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023	215*	2023
Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning accelerators J Zhang, K Rangineni, Z Ghodsi, S Garg Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018	178	2018
Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator JJ Zhang, T Gu, K Basu, S Garg 2018 IEEE 36th VLSI Test Symposium (VTS), 1-6, 2018	177	2018
Chip-chat: Challenges and opportunities in conversational hardware design J Blocklove, S Garg, R Karri, H Pearce 2023 ACM/IEEE 5th Workshop on Machine Learning for CAD (MLCAD), 1-6, 2023	154	2023
Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors B Raghunathan, Y Turakhia, S Garg, D Marculescu 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 39-44, 2013	148	2013
Lost at c: A user study on the security implications of large language model code assistants G Sandoval, H Pearce, T Nys, R Karri, S Garg, B Dolan-Gavitt 32nd USENIX Security Symposium (USENIX Security 23), 2205-2222, 2023	127	2023
Reverse engineering camouflaged sequential circuits without scan access M El Massad, S Garg, M Tripunitara 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 33-40, 2017	119	2017
Deepreduce: Relu reduction for fast private inference NK Jha, Z Ghodsi, S Garg, B Reagen International Conference on Machine Learning, 4839-4849, 2021	103	2021
Securing hardware accelerators: A new challenge for high-level synthesis C Pilato, S Garg, K Wu, R Karri, F Regazzoni IEEE Embedded Systems Letters 10 (3), 77-80, 2017	103	2017
Cryptonas: Private inference on a relu budget Z Ghodsi, AK Veldanda, B Reagen, S Garg Advances in Neural Information Processing Systems 33, 16961-16971, 2020	96	2020
Verifiable asics RS Wahby, M Howald, S Garg, A Shelat, M Walfish 2016 IEEE Symposium on Security and Privacy (SP), 759-778, 2016	93*	2016
Fault-tolerant systolic array based accelerators for deep neural network execution JJ Zhang, K Basu, S Garg IEEE Design & Test 36 (5), 44-53, 2019	86	2019
HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors Y Turakhia, B Raghunathan, S Garg, D Marculescu Proceedings of the 50th Annual Design Automation Conference, 1-7, 2013	81	2013

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