| A critical review on performance, reliability, and fabrication challenges in nanosheet FET for future analog/digital IC applications S Valasa, S Tayal, LR Thoutam, J Ajayan, S Bhattacharya Micro and Nanostructures 170, 207374, 2022 | 32 | 2022 |
| Optimization of design space for vertically stacked junctionless nanosheet FET for analog/RF applications S Valasa, S Tayal, LR Thoutam Silicon 14 (16), 10347-10356, 2022 | 27 | 2022 |
| Investigation of nanosheet-FET based logic gates at sub-7 nm technology node for digital IC applications S Tayal, S Valasa, S Bhattacharya, J Ajayan, SM Ahmed, B Jena, ... Silicon 14 (18), 12261-12267, 2022 | 26 | 2022 |
| An intensive study of tree-shaped JL-NSFET: digital and analog/RF perspective S Valasa, S Tayal, LR Thoutam IEEE Transactions on Electron Devices 69 (12), 6561-6568, 2022 | 24 | 2022 |
| Design insights into thermal performance of vertically stacked JL-NSFET with high-k gate dielectric for sub 5-nm technology node S Valasa, S Tayal, LR Thoutam ECS Journal of Solid State Science and Technology 11 (4), 041008, 2022 | 21 | 2022 |
| Beyond Moore's law – A critical review of advancements in negative capacitance field effect transistors: A revolution in next-generation electronics S Valasa, VR Kotha, N Vadthiya Materials Science in Semiconductor Processing 173, 108116, 2024 | 16 | 2024 |
| Design and performance optimization of junctionless bottom spacer FinFET for digital/analog/RF applications at sub-5nm technology node S Valasa, KV Ramakrishna, N Vadthiya, S Bhukya, NB Rao, ... ECS Journal of Solid State Science and Technology 12 (1), 013004, 2023 | 15 | 2023 |
| Performance analysis of metal gate engineered junctionless nanosheet fet with a ft/fmax of 224/342ghz for beyond 5g (b5g) applications S Valasa, S Tayal, LR Thoutam Micro and Nanostructures 179, 207582, 2023 | 14 | 2023 |
| Performance evaluation of spacer dielectric engineered vertically stacked junctionless nanosheet FET for sub-5 nm technology node S Valasa, S Tayal, LR Thoutam ECS Journal of Solid State Science and Technology 11 (9), 093006, 2022 | 14 | 2022 |
| A proposal for optimization of spacer engineering at Sub-5-nm technology node for JL-TreeFET: a device to circuit level implementation R Andavarapu, S Bagati, S Valasa, VR Kotha, S Bhukya, SK Padhi, ... IEEE Transactions on Electron Devices 71 (1), 453-460, 2023 | 13 | 2023 |
| Optimizing U-Shape FinFETs for Sub-5nm technology: performance analysis and device-to-circuit evaluation in digital and analog/radio frequency applications KV Ramakrishna, S Valasa, S Bhukya, N Vadthiya ECS Journal of Solid State Science and Technology 12 (9), 093007, 2023 | 12 | 2023 |
| A power and delay efficient circuit for CMOS phase detector and phase frequency detector S Valasa, JR Shinde, DR Ramji, S Avunoori 2021 6th international conference on communication and electronics systems …, 2021 | 11 | 2021 |
| Performance analysis of dielectrically separated independent gates junctionless DG-MOSFET: a digital perspective N Guduri, D Kannuri, RR Maram, NK Kevuloth, S Valasa, S Tayal 2022 IEEE International Conference on Nanoelectronics, Nanophotonics …, 2022 | 10 | 2022 |
| Pushing the boundaries: Design and simulation approach of negative capacitance nanosheet FETs with ferroelectric and dielectric spacers at the sub-3 nm technology node for … S Valasa, VR Kotha, N Vadthiya ACS Applied Electronic Materials 6 (5), 3206-3215, 2024 | 7 | 2024 |
| Performance investigation of FinFET structures: unleashing multi-gate control through design and simulation at the 7 nm technology node for next-generation electronic devices S Valasa, KV Ramakrishna, S Bhukya, P Narware, V Bheemudu, ... ECS Journal of Solid State Science and Technology 12 (11), 113012, 2023 | 3 | 2023 |
| Impact of Channel Thickness on the Performance of JL-DG MOSFET based NAND, NOR, and NOT Logic Gates S Katharashala, S Gandla, V Bommineni, S Tayal, S Valasa, J Ajayan 2022 IEEE International Conference on Nanoelectronics, Nanophotonics …, 2022 | 3 | 2022 |
| On-the-fly key generation based VLSI implementation of advanced encryption standard S Valasa, S Avunoori, JR Shinde 2021 6th International Conference on Communication and Electronics Systems …, 2021 | 3 | 2021 |
| Interface traps in the sub-3 nm technology node: A comprehensive analysis and benchmarking of negative capacitance FinFET and nanosheet FETs-A reliability perspective from … S Valasa, VR Kotha, N Vadthiya Microelectronics Reliability 160, 115479, 2024 | 2 | 2024 |
| Design Space Optimization for Eradication of NDR Effect in Dielectric/Ferroelectric Stacked Negative Capacitance Multi-Gate FETs at Sub-3nm Technology for Digital/Analog/RF … S Valasa, VR Kotha, S Tayal, N Vadthiya IEEE Transactions on Dielectrics and Electrical Insulation, 2024 | 2 | 2024 |
| Design considerations into circuit applications for structurally optimised FinFET K Sarangam, S Valasa, PK Mudidhe, V Narendar, VR Kotha, S Bhukya, ... ECS Journal of Solid State Science and Technology 12 (12), 123007, 2023 | 2 | 2023 |
Shubham TayalSynopsys India Pvt. Ltd., HyderabadVerifisert e-postadresse på nitkkr.ac.in