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Jae-Joon Kim
Jae-Joon Kim
Professor, Seoul National University
Verifisert e-postadresse på snu.ac.kr - Startside
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A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS
IJ Chang, JJ Kim, SP Park, K Roy
IEEE Journal of Solid-State Circuits 44 (2), 650-658, 2009
6652009
Sense-amp based adder with source follower evaluation tree
JJ Kim, CTK Chuang, RV Joshi, K Roy
US Patent 6,789,099, 2004
3982004
Double gate-MOSFET subthreshold circuit for ultralow power applications
JJ Kim, K Roy
IEEE Transactions on Electron Devices 51 (9), 1468-1474, 2004
1662004
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations
CH Kim, JJ Kim, S Mukhopadhyay, K Roy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (3), 349-357, 2005
1382005
Negative Transconductance Heterojunction Organic Transistors and their Application to Full-Swing Ternary Circuits
H Yoo, S On, SB Lee, K Cho, JJ Kim
Advanced Materials, 2019
1132019
Back-gate controlled read SRAM cell
JJ Kim, K Kim
US Patent 7,177,177, 2007
1072007
Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability
A Bansal, R Rao, JJ Kim, S Zafar, JH Stathis, CT Chuang
Microelectronics reliability 49 (6), 642-649, 2009
1042009
Area-efficient and variation-tolerant in-memory BNN computing using 6T SRAM array
J Kim, J Koo, T Kim, Y Kim, H Kim, S Yoo, JJ Kim
2019 Symposium on VLSI Circuits, C118-C119, 2019
1012019
BitBlade: Area and Energy-Efficient Precision-Scalable Neural Network Accelerator with Bitwise Summation
S Ryu, H Kim, W Yi, JJ Kim
Proceedings of the 56th Annual Design Automation Conference (DAC), 2019
902019
SRAM write-ability improvement with transient negative bit-line voltage
S Mukhopadhyay, RM Rao, JJ Kim, CT Chuang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (1), 24-32, 2009
902009
Monolithically integrated RRAM-and CMOS-based in-memory computing optimizations for efficient deep learning
S Yin, Y Kim, X Han, H Barnaby, S Yu, Y Luo, W He, X Sun, JJ Kim, J Seo
IEEE Micro 39 (6), 54-63, 2019
892019
High-performance SRAM in nanoscale CMOS: Design challenges and techniques
CT Chuang, S Mukhopadhyay, JJ Kim, K Kim, R Rao
2007 IEEE international workshop on memory technology, design and testing, 4-12, 2007
882007
A forward body-biased low-leakage SRAM cache: device and architecture considerations
CH Kim, JJ Kim, S Mukhopadhyay, K Roy
Proceedings of the 2003 international symposium on Low power electronics and …, 2003
792003
Improved synapse device with MLC and conductance linearity using quantized conduction for neuromorphic systems
S Lim, C Sung, H Kim, T Kim, J Song, JJ Kim, H Hwang
IEEE Electron Device Letters 39 (2), 312-315, 2018
742018
8.2 8Mb/s 28Mb/mJ robust true-random-number generator in 65nm CMOS based on differential ring oscillator with feedback resistors
E Kim, M Lee, JJ Kim
2017 IEEE International Solid-State Circuits Conference (ISSCC), 144-145, 2017
722017
PVT-aware leakage reduction for on-die caches with improved read stability
CH Kim, JJ Kim, IJ Chang, K Roy
IEEE Journal of Solid-State Circuits 41 (1), 170-178, 2006
632006
2-bit-per-cell RRAM-based in-memory computing for area-/energy-efficient deep learning
W He, S Yin, Y Kim, X Sun, JJ Kim, S Yu, JS Seo
IEEE Solid-State Circuits Letters 3, 194-197, 2020
622020
Unifying activation-and timing-based learning rules for spiking neural networks
J Kim, K Kim, JJ Kim
Advances in neural information processing systems 33, 19534-19544, 2020
552020
OPTIMUS: OPTImized matrix MUltiplication Structure for Transformer neural network accelerator
J Park, H Yoon, D Ahn, J Choi, JJ Kim
Proceedings of Machine Learning and Systems 2, 363-378, 2020
532020
Binaryduo: Reducing gradient mismatch in binary activation network by coupling binary activations
H Kim, K Kim, J Kim, JJ Kim
arXiv preprint arXiv:2002.06517, 2020
532020
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Artikler 1–20