Obstacle detection and classification using deep learning for tracking in high-speed autonomous driving G Prabhakar, B Kailath, S Natarajan, R Kumar
2017 IEEE region 10 symposium (TENSYMP), 1-6, 2017
158 2017 A novel phase frequency detector for a high frequency PLL design KKA Majeed, BJ Kailath
Procedia Engineering 64, 377-384, 2013
53 2013 Low power, high frequency, free dead zone PFD for a PLL design KKA Majeed, BJ Kailath
2013 IEEE Faible Tension Faible Consommation, 1-4, 2013
52 2013 Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP KK Abdul Majeed, BJ Kailath
Analog Integrated Circuits and Signal Processing 93, 29-39, 2017
38 2017 Design of optimized MAC unit using integrated vedic multiplier M Yuvaraj, BJ Kailath, N Bhaskhar
2017 International conference on Microelectronic Devices, Circuits and …, 2017
25 2017 PLL architecture with a composite PFD and variable loop filter AM KK, BJ Kailath
IET Circuits, Devices & Systems 12 (3), 256-262, 2018
20 2018 CMOS current starved voltage controlled oscillator circuit for a fast locking PLL AM KK, BJ Kailath
2015 Annual IEEE India Conference (INDICON), 1-5, 2015
20 2015 Analysis and design of low power nonlinear PFD architectures for a fast locking PLL KKA Majeed, BJ Kailath
2016 IEEE Students’ Technology Symposium (TechSym), 136-140, 2016
19 2016 Fast and accurate on-road vehicle detection based on color intensity segregation MS Sravan, S Natarajan, ES Krishna, BJ Kailath
Procedia computer science 133, 594-603, 2018
15 2018 Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur AMK Kuppalath, BJ Kailath
IEICE Electronics Express 13 (10), 20160328-20160328, 2016
11 2016 Electrical and Reliability Characteristics of MOS Devices With Ultrathin BJ Kailath, A DasGupta, N DasGupta
IEEE Transactions on Device and Materials Reliability 7 (4), 602-610, 2007
11 2007 Optimized MAC unit design S Deepak, BJ Kailath
2012 IEEE international conference on electron devices and solid state …, 2012
9 2012 Optimisation of ac anodisation parameters for the improvement of electrical properties of thermally grown ultrathin gate oxide BJ Kailath, A DasGupta, N DasGupta
Solid-state electronics 51 (5), 762-770, 2007
9 2007 High speed Power efficient Vedic arithmetic modules on Zedboard‐Zynq‐7000 FPGA. BJ Kailath
International Journal of Circuit Theory & Applications 49 (11), 2021
6 2021 A novel method to implement STDP learning rule in verilog A Manoharan, G Muralidhar, BJ Kailath
2020 IEEE Region 10 Symposium (TENSYMP), 1779-1782, 2020
6 2020 Composite PFD based low-power, low noise, fast lock-in PLL BJ Kailath, KK Majeed
5 2019 Bistable-triplet stdp circuit without external memory for integrating with silicon neurons BJ Kailath
2021 IEEE World AI IoT Congress (AIIoT), 0297-0302, 2021
4 2021 Accelerating occupancy grid map computation with gpu for real-time obstacle detection S Natarajan, BJ Kailath, D Kumar, R Kumar
2016 22nd Annual International Conference on Advanced Computing and …, 2016
4 2016 16-bit Modified Vedic Paravartya Divider with quotient in fractions MKS Vikasini, BJ Kailath
2021 IEEE Region 10 Symposium (TENSYMP), 1-5, 2021
3 2021 Graph-Based Circuit Simulator for Switched Capacitor Circuits G Dinesh, BJ Kailath
IEEE Design & Test 39 (4), 81-89, 2021
3 2021 
Dr Abdul Majeed K KVellore Institute of Technology ( VIT ) VelloreVerifisert e-postadresse på vit.ac.in
