| FinFET-a self-aligned double-gate MOSFET scalable to 20 nm D Hisamoto, WC Lee, J Kedzierski, H Takeuchi, K Asano, C Kuo, ... IEEE transactions on electron devices 47 (12), 2320-2325, 2000 | 2435 | 2000 |
| Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec WY Choi, BG Park, JD Lee, TJK Liu IEEE Electron Device Letters 28 (8), 743-745, 2007 | 2123 | 2007 |
| FinFET scaling to 10 nm gate length B Yu, L Chang, S Ahmed, H Wang, S Bell, CY Yang, C Tabery, C Ho, ... Digest. International Electron Devices Meeting,, 251-254, 2002 | 876 | 2002 |
| Sub 50-nm finfet: Pmos X Huang, WC Lee, C Kuo, D Hisamoto, L Chang, J Kedzierski, ... International Electron Devices Meeting 1999. Technical Digest (Cat. No …, 1999 | 846 | 1999 |
| Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture C Hu, TJ King, V Subramanian, L Chang, X Huang, YK Choi, ... US Patent 6,413,802, 2002 | 682 | 2002 |
| Sub-50 nm P-channel FinFET X Huang, WC Lee, C Kuo, D Hisamoto, L Chang, J Kedzierski, ... IEEE Transactions on Electron Devices 48 (5), 880-886, 2001 | 618 | 2001 |
| Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology YC Yeo, TJ King, C Hu Journal of applied physics 92 (12), 7266-7271, 2002 | 565 | 2002 |
| The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance T Skotnicki, JA Hutchby, TJ King, HSP Wong, F Boeuf IEEE Circuits and Devices Magazine 21 (1), 16-26, 2005 | 562 | 2005 |
| Evidence for Higgs boson decay to a pair of muons AM Sirunyan, A Tumasyan, W Adam, T Bergauer, M Dragicevic, J Erö, ... Journal of High Energy Physics 2021 (1), 1-68, 2021 | 553* | 2021 |
| Frequency-independent equivalent-circuit model for on-chip spiral inductors Y Cao, RA Groves, X Huang, ND Zamdmer, JO Plouchart, RA Wachnik, ... IEEE Journal of solid-state circuits 38 (3), 419-426, 2003 | 538 | 2003 |
| Sub-20 nm CMOS FinFET technologies YK Choi, N Lindert, P Xuan, S Tang, D Ha, E Anderson, TJ King, J Bokor, ... International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001 | 463 | 2001 |
| Germanium-source tunnel field effect transistors with record high ION/IOFF SH Kim, H Kam, C Hu, TJK Liu 2009 Symposium on VLSI Technology, 178-179, 2009 | 440 | 2009 |
| A folded-channel MOSFET for deep-sub-tenth micron era D Hisamoto, WC Lee, J Kedzierski, E Anderson, H Takeuchi, K Asano, ... IEDM Tech. Dig 1998, 1032-1034, 1998 | 427 | 1998 |
| Segmented channel MOS transistor TJ King, V Moroz US Patent 7,247,887, 2007 | 412 | 2007 |
| Methods of designing an integrated circuit on corrugated substrate TJ King, V Moroz US Patent 7,960,232, 2011 | 411 | 2011 |
| Ultra-thin body SOI MOSFET for deep-sub-tenth micron era YK Choi, K Asano, N Lindert, V Subramanian, TJ King, J Bokor, C Hu International Electron Devices Meeting 1999. Technical Digest (Cat. No …, 1999 | 385 | 1999 |
| Extremely scaled silicon nano-CMOS devices L Chang, Y Choi, D Ha, P Ranade, S Xiong, J Bokor, C Hu, TJ King Proceedings of the IEEE 91 (11), 1860-1873, 2003 | 378 | 2003 |
| A spacer patterning technology for nanoscale CMOS YK Choi, TJ King, C Hu IEEE Transactions on Electron Devices 49 (3), 436-441, 2002 | 370 | 2002 |
| Nanoscale CMOS spacer FinFET for the terabit era YK Choi, TJ King, C Hu IEEE Electron Device Letters 23 (1), 25-27, 2002 | 347 | 2002 |
| Integrated circuit on corrugated substrate TJ King, V Moroz US Patent 7,190,050, 2007 | 342 | 2007 |
chenming huUniversity of California, BerkeleyVerifisert e-postadresse på eecs.berkeley.edu
