| Out-of-order parallel simulation for ESL design W Chen, X Han, R Dömer Proceedings of the Conference on Design, Automation and Test in Europe, 141-146, 2012 | 53 | 2012 |
| A graph reduction approach to symbolic circuit analysis CJR Shi 2007 Asia and South Pacific Design Automation Conference, 197-202, 2007 | 41 | 2007 |
| Multi-core parallel simulation of system-level description languages R Dömer, W Chen, X Han, A Gerstlauer Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific …, 2011 | 40 | 2011 |
| Out-of-Order Parallel Discrete Event Simulation for Transaction Level Models W Chen, X Han, C Chang, G Liu, R Domer Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2014 | 32 | 2014 |
| Multicore simulation of transaction-level models using the soc environment W Chen, X Han, R Doemer IEEE Design & Test of Computers, 20-31, 2011 | 30 | 2011 |
| Implementation of a symbolic circuit simulator for topological network analysis W Chen, G Shi Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on …, 2006 | 30 | 2006 |
| Optimized out-of-order parallel discrete event simulation using predictions W Chen, R Dömer Proceedings of the Conference on Design, Automation and Test in Europe, 3-8, 2013 | 28 | 2013 |
| May-happen-in-parallel analysis based on segment graphs for safe ESL models W Chen, X Han, R Dömer Proceedings of the conference on Design, Automation & Test in Europe, 287, 2014 | 26 | 2014 |
| An inter-core communication enabled multi-core simulator based on simplescalar R Zhong, Y Zhu, W Chen, M Lin, WF Wong Advanced Information Networking and Applications Workshops, 2007, AINAW'07 …, 2007 | 25 | 2007 |
| Parallel discrete event simulation of Transaction Level Models R Dömer, W Chen, X Han Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific …, 2012 | 22 | 2012 |
| ESL design and multi-core validation using the system-on-chip environment W Chen, X Han, R Dömer High Level Design Validation and Test Workshop (HLDVT), 2010 IEEE …, 2010 | 13 | 2010 |
| An optimizing compiler for out-of-order parallel ESL simulation exploiting instance isolation W Chen, R Dömer Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific …, 2012 | 12 | 2012 |
| Out-of-order Parallel Discrete Event Simulation for Electronic System-level Design W Chen Springer, 2014 | 8 | 2014 |
| Advances in Parallel Discrete Event Simulation for Electronic System-Level Design W Chen, X Han, CW Chang, R Dömer IEEE Design and Test of Computers 30 (1), 45-54, 2013 | 8 | 2013 |
| Eliminating race conditions in system-level models by using parallel simulation infrastructure W Chen, CW Chang, X Han, R Domer High Level Design Validation and Test Workshop (HLDVT), 2012 IEEE …, 2012 | 7 | 2012 |
| A Parallel Transaction-Level Model of H. 264 Video Decoder X Han, W Chen, R Doemer Center for Embedded Computer Systems, 2011 | 6 | 2011 |
| A Distributed Parallel Simulator for Transaction Level Models with Relaxed Timing W Chen, R Dömer Center for Embedded Computer Systems, University of California, Technical Report, 2011 | 4 | 2011 |
| ConcurrenC: A new approach towards effective abstraction of C-based SLDLs W Chen, R Dömer Analysis, Architectures and Modelling of Embedded Systems, 57-65, 2009 | 3 | 2009 |
| Designer-in-the-loop recoding of ESL models using static parallel access conflict analysis X Han, W Chen, R Dömer Proceedings of the 16th International Workshop on Software and Compilers for …, 2013 | 2 | 2013 |
| System Level Modeling of a H. 264 Decoder W Chen, S Sun, B Zhang, R Dömer Center for Embedded Computer Systems, 2008 | 1 | 2008 |
Rainer DoemerProfessor, University of California, IrvineVerifisert e-postadresse på uci.edu