| Phase tracking and prediction T Sherwood, S Sair, B Calder ACM SIGARCH Computer Architecture News 31 (2), 336-349, 2003 | 671 | 2003 |
| Discovering and exploiting program phases T Sherwood, E Perelman, G Hamerly, S Sair, B Calder IEEE micro 23 (6), 84-93, 2003 | 388 | 2003 |
| Pointer cache assisted prefetching J Collins, S Sair, B Calder, DM Tullsen 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002 …, 2002 | 209 | 2002 |
| Predictor-directed stream buffers T Sherwood, S Sair, B Calder Proceedings of the 33rd annual ACM/IEEE international symposium on …, 2000 | 169 | 2000 |
| Memory behavior of the SPEC2000 benchmark suite S Sair, M Charney Technical report, IBM TJ Watson Research Center, 2000 | 145 | 2000 |
| Vector friendly instruction format and execution thereof RC Valentine, JC San Adrian, RE Sans, RD Cavin, BL Toll, SG Duran, ... US Patent App. 13/976,707, 2013 | 127 | 2013 |
| A decoupled predictor-directed stream prefetching architecture S Sair, T Sherwood, B Calder IEEE Transactions on Computers 52 (3), 260-276, 2003 | 49 | 2003 |
| Gather-op instruction to duplicate a mask and perform an operation on vector elements gathered via tracked offset-based gathering E Ould-Ahmed-Vall, KA Doshi, CR Yount, S Sair US Patent 9,747,101, 2017 | 41 | 2017 |
| Catching accurate profiles in hardware S Narayanasamy, T Sherwood, S Sair, B Calder, G Varghese The Ninth International Symposium on High-Performance Computer Architecture …, 2003 | 37 | 2003 |
| Instruction and logic to provide stride-based vector load-op functionality with mask duplication E Ould-Ahmed-Vall, KA Doshi, S Sair, CR Yount US Patent 9,804,844, 2017 | 30 | 2017 |
| Instruction and logic to provide vector horizontal majority voting functionality E Ould-Ahmed-Vall, KA Doshi, S Sair, CR Yount US Patent 9,448,794, 2016 | 30 | 2016 |
| Efficient zero-based decompression E Ould-Ahmed-Vall, S Sair, KA Doshi, CR Yount, BL Toll US Patent 9,575,757, 2017 | 28 | 2017 |
| Low-overhead core swapping for thermal management E Kursun, G Reinman, S Sair, A Shayesteh, T Sherwood Power-Aware Computer Systems: 4th International Workshop, PACS 2004 …, 2005 | 28 | 2005 |
| Vector instruction for presenting complex conjugates of respective complex numbers S Sair, E Ould-Ahmed-Vall US Patent 9,411,583, 2016 | 25 | 2016 |
| Quantifying load stream behavior S Sair, T Sherwood, B Calder Proceedings Eighth International Symposium on High Performance Computer …, 2002 | 24 | 2002 |
| Persistent Remote Direct Memory Access K Kumar, S Sair, FG Bernat, T Willhalm, DR BARRAGAN US Patent App. 15/435,886, 2018 | 21 | 2018 |
| System, apparatus and method for loop remainder mask instruction E Ould-Ahmed-Vall, R Valentine, J Corbal, A Naraikin, S Sair, A Hargil, ... US Patent App. 13/993,323, 2014 | 20 | 2014 |
| Reducing the latency and area cost of core swapping through shared helper engines A Shayesteh, E Kursun, T Sherwood, S Sair, G Reinman 2005 International Conference on Computer Design, 17-23, 2005 | 19 | 2005 |
| Designing real-time h. 264 decoders with dataflow architectures Y Kim, S Sair Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware …, 2005 | 19 | 2005 |
| Vector friendly instruction format and execution thereof RC Valentine, JC San Adrian, RE Sans, RD Cavin, BL Toll, SG Duran, ... US Patent 9,513,917, 2016 | 17 | 2016 |
