| Throughput-optimized OpenCL-based FPGA accelerator for large-scale convolutional neural networks N Suda, V Chandra, G Dasika, A Mohanty, Y Ma, S Vrudhula, J Seo, ... Proceedings of the 2016 ACM/SIGDA international symposium on field …, 2016 | 729 | 2016 |
| Optimizing loop operation and dataflow in FPGA acceleration of deep convolutional neural networks Y Ma, Y Cao, S Vrudhula, J Seo Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017 | 485 | 2017 |
| Optimizing the convolution operation to accelerate deep neural networks on FPGA Y Ma, Y Cao, S Vrudhula, J Seo IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (7 …, 2018 | 384 | 2018 |
| Scalable and modularized RTL compilation of convolutional neural networks onto FPGA Y Ma, N Suda, Y Cao, J Seo, S Vrudhula 2016 26th international conference on field programmable logic and …, 2016 | 226 | 2016 |
| An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks Y Ma, Y Cao, S Vrudhula, J Seo 2017 27th International Conference on Field Programmable Logic and …, 2017 | 180 | 2017 |
| ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler Y Ma, N Suda, Y Cao, S Vrudhula, J Seo Integration 62, 14-23, 2018 | 123 | 2018 |
| End-to-end scalable FPGA accelerator for deep residual networks Y Ma, M Kim, Y Cao, S Vrudhula, J Seo 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 74 | 2017 |
| Performance modeling for CNN inference accelerators on FPGA Y Ma, Y Cao, S Vrudhula, JS Seo IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 73 | 2019 |
| Automatic compilation of diverse CNNs onto high-performance FPGA accelerators Y Ma, Y Cao, S Vrudhula, J Seo IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 64 | 2018 |
| Automatic compiler based FPGA accelerator for CNN training SK Venkataramanaiah, Y Ma, S Yin, E Nurvithadhi, A Dasu, Y Cao, J Seo 2019 29th International Conference on Field Programmable Logic and …, 2019 | 60 | 2019 |
| A flexible and efficient FPGA accelerator for various large-scale and lightweight CNNs X Wu, Y Ma, M Wang, Z Wang IEEE Transactions on Circuits and Systems I: Regular Papers 69 (3), 1185-1198, 2021 | 57 | 2021 |
| Algorithm-hardware co-design of single shot detector for fast object detection on FPGAs Y Ma, T Zheng, Y Cao, S Vrudhula, J Seo 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 39 | 2018 |
| 7.8 A 22nm delta-sigma computing-in-memory (Δ∑ CIM) SRAM macro with near-zero-mean outputs and LSB-first ADCs achieving 21.38 TOPS/W for 8b-MAC edge AI processing P Chen, M Wu, W Zhao, J Cui, Z Wang, Y Zhang, Q Wang, J Ru, L Shen, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 140-142, 2023 | 27 | 2023 |
| In-memory computing: The next-generation ai computing paradigm Y Ma, Y Du, L Du, J Lin, Z Wang Proceedings of the 2020 on Great Lakes Symposium on VLSI, 265-270, 2020 | 24 | 2020 |
| An efficient FPGA accelerator optimized for high throughput sparse CNN inference J Wen, Y Ma, Z Wang 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 165-168, 2020 | 19 | 2020 |
| Efficient hardware post processing of anchor-based object detection on FPGA H Zhang, W Wu, Y Ma, Z Wang 2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 580-585, 2020 | 18 | 2020 |
| Efficient network construction through structural plasticity X Du, Z Li, Y Ma, Y Cao IEEE Journal on Emerging and Selected Topics in Circuits and Systems 9 (3 …, 2019 | 17 | 2019 |
| Hybrid stochastic-binary computing for low-latency and high-precision inference of CNNs Z Chen, Y Ma, Z Wang IEEE Transactions on Circuits and Systems I: Regular Papers 69 (7), 2707-2720, 2022 | 16 | 2022 |
| Small-world-based structural pruning for efficient FPGA inference of deep neural networks G Krishnan, Y Ma, Y Cao 2020 IEEE 15th International Conference on Solid-State & Integrated Circuit …, 2020 | 11 | 2020 |
| RIMAC: An array-level ADC/DAC-free ReRAM-based in-memory DNN processor with analog cache and computation P Chen, M Wu, Y Ma, L Ye, R Huang Proceedings of the 28th Asia and South Pacific Design Automation Conference …, 2023 | 9 | 2023 |
Jae-sun SeoCornell TechZweryfikowany adres z cornell.edu