| Bit parallel 6T SRAM in-memory computing with reconfigurable bit-precision K Lee, J Jeong, S Cheon, W Choi, J Park 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 66 | 2020 |
| Content addressable memory based binarized neural network accelerator using time-domain signal processing W Choi, K Jeong, K Choi, K Lee, J Park Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 30 | 2018 |
| Low cost ternary content addressable memory using adaptive matchline discharging scheme W Choi, K Lee, J Park 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2018 | 28 | 2018 |
| A charge-sharing based 8t sram in-memory computing for edge dnn acceleration K Lee, S Cheon, J Jo, W Choi, J Park 2021 58th ACM/IEEE Design Automation Conference (DAC), 739-744, 2021 | 18 | 2021 |
| A 2941-TOPS/W charge-domain 10T SRAM compute-in-memory for ternary neural network S Cheon, K Lee, J Park IEEE Transactions on Circuits and Systems I: Regular Papers 70 (5), 2085-2097, 2023 | 16 | 2023 |
| Low cost ternary content addressable memory based on early termination precharge scheme K Lee, G Ko, J Park 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2019 | 12 | 2019 |
| Low-cost 7t-sram compute-in-memory design based on bit-line charge-sharing based analog-to-digital conversion K Lee, J Kim, J Park Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022 | 9 | 2022 |
| A 65-nm 0.6-fJ/Bit/Search ternary content addressable memory using an adaptive match-line discharge K Lee, W Choi, J Park IEEE Journal of Solid-State Circuits 56 (8), 2574-2584, 2020 | 7 | 2020 |
| A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC Operations K Lee, J Kim, J Park IEEE Journal of Solid-State Circuits, 2023 | 6 | 2023 |
| A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing J Kim, K Lee, J Park Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …, 2022 | 6 | 2022 |
| A 10T SRAM compute-in-memory macro with analog MAC operation and time domain conversion H Park, K Lee, J Park 2022 IEEE 4th International Conference on Artificial Intelligence Circuits …, 2022 | 3 | 2022 |
| Low Area and Low Power Threshold Implementation Design Technique for AES S-Box J Song, K Lee, J Park IEEE Transactions on Circuits and Systems II: Express Briefs 70 (3), 1169-1173, 2022 | 1 | 2022 |
| Computing-in-memory device including digital-to-analog converter based on memory structure J Park, J Kim, KH Lee US Patent App. 18/342,013, 2024 | | 2024 |
| Computing in memory electronic device capable of supporting current based analog multiply-accumulation operations and time based analog-to-digital conversion J Park, P Hyunchul, K Lee US Patent App. 17/987,072, 2023 | | 2023 |
| Sram cell configured to perform multiply-accumulate (mac) operation on multi-bit data based on charge sharing and method of operating the same J Park, K Lee, H Kim US Patent App. 18/180,623, 2023 | | 2023 |
| Memory device supporting in-memory mac operation between ternary input data and binary weight using charge sharing method and operation method thereof J Park, SS Cheon, KH Lee US Patent App. 18/101,287, 2023 | | 2023 |
| In-memory computing device supporting arithmetic operations J Park, K Lee, W Choi US Patent 11,664,069, 2023 | | 2023 |
| Computing in-memory device supporting arithmetic operations and method of controlling the same J Park, K Lee, W Choi US Patent 11,626,159, 2023 | | 2023 |
Jongsun ParkProfessor of Electrical Engineering, Korea UniversityZweryfikowany adres z korea.ac.kr