| Catena: A near-threshold, sub-0.4-mW, 16-core programmable spatial array accelerator for the ultralow-power mobile and embedded Internet of Things JP Cerqueira, TJ Repetti, Y Pu, S Priyadarshi, MA Kim, M Seok IEEE Journal of Solid-State Circuits 55 (8), 2270-2284, 2020 | 21 | 2020 |
| Master of none acceleration: A comparison of accelerator architectures for analytical query processing A Lottarini, JP Cerqueira, TJ Repetti, SA Edwards, KA Ross, M Seok, ... Proceedings of the 46th International Symposium on Computer Architecture …, 2019 | 21 | 2019 |
| Pipelining a triggered processing element TJ Repetti, JP Cerqueira, MA Kim, M Seok Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 20 | 2017 |
| Catena: A 0.5-V Sub-0.4-mW 16-core spatial array accelerator for mobile and embedded computing JP Cerqueira, TJ Repetti, Y Pu, S Priyadarshi, MA Kim, M Seok 2019 Symposium on VLSI Circuits, C54-C55, 2019 | 10 | 2019 |
| Designing, Implementing and Programming a Massively Multithreaded Spatial Accelerator Architecture TJ Repetti Columbia University, 2023 | | 2023 |
| A Case Study in Optimizing HTM-Enabled Dynamic Data Structures: Patricia Tries TJRMP Herlihy | | |
