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Nithin George
Nithin George
Intel Corporation (previously, École Polytechnique Fédérale de Lausanne)
Zweryfikowany adres z intel.com
Tytuł
Cytowane przez
Cytowane przez
Rok
Hardware system synthesis from domain-specific languages
N George, HJ Lee, D Novo, T Rompf, KJ Brown, AK Sujeeth, M Odersky, ...
2014 24th International Conference on Field Programmable Logic and …, 2014
922014
Virtualized execution runtime for FPGA accelerators in the cloud
M Asiatici, N George, K Vipin, SA Fahmy, P Ienne
Ieee Access 5, 1900-1910, 2017
892017
SuSy: A programming model for productive construction of high-performance systolic arrays on FPGAs
YH Lai, H Rong, S Zheng, W Zhang, X Cui, Y Jia, J Wang, B Sullivan, ...
Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020
592020
Design space exploration of LDPC decoders using high-level synthesis
J Andrade, N George, K Karras, D Novo, F Pratas, L Sousa, P Ienne, ...
IEEE Access 5, 14600-14615, 2017
302017
Making domain-specific hardware synthesis tools cost-efficient
N George, D Novo, T Rompf, M Odersky, P Ienne
2013 International Conference on Field-Programmable Technology (FPT), 120-127, 2013
292013
Designing a virtual runtime for FPGA accelerators in the cloud
M Asiatici, N George, K Vipin, SA Fahmy, P Ienne
2016 26th international conference on field programmable logic and …, 2016
172016
From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis
J Andrade, N George, K Karras, D Novo, V Silva, P Ienne, G Falcão
2015 25th International Conference on Field Programmable Logic and …, 2015
142015
Enriching C-based High-Level Synthesis with parallel pattern templates
L Josipovic, N George, P Ienne
2016 International Conference on Field-Programmable Technology (FPT), 177-180, 2016
122016
Automatic support for multi-module parallelism from computational patterns
N George, HJ Lee, D Novo, M Owaida, D Andrews, K Olukotun, P Ienne
2015 25th International Conference on Field Programmable Logic and …, 2015
122015
Fast design space exploration using vivado HLS: Non-binary LDPC decoders
J Andrade, N George, K Karras, D Novo, V Silva, P Ienne, G Falcao
2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom …, 2015
102015
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs
YOM Moctar, N George, H Parandeh-Afshar, P Ienne, GGF Lemieux, ...
Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012
102012
CodePin: An Instrumentation-Based Debug Tool of SYCLomatic
A Huang, Z Wang, W Ni, S Chen, N George
Proceedings of the 12th International Workshop on OpenCL and SYCL, 1-2, 2024
2024
SuSy
YH Lai, H Rong, S Zheng, W Zhang, X Cui, Y Jia, J Wang, B Sullivan, ...
Proceedings of the 39th International Conference on Computer-Aided Design, 2020
2020
FPGAs for the Masses: Affordable Hardware Synthesis from Domain-Specific Languages
N George
EPFL, 2016
2016
LAP
M Asiatici, K Atasu, P Athanasopoulos, AG Bayrak, AJ Becker, R Beuchat, ...
Heterogeneity and Reconfigurability as Key Enablers for Energy Efficient Computing
N George
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