| OuterSPACE: An Outer Product based Sparse Matrix Multiplication Accelerator S Pal, J Beaumont, DH Park, A Amarnath, S Feng, C Chakrabarti, HS Kim, ... 2018 IEEE International Symposium on High Performance Computer Architecture …, 2018 | 313 | 2018 |
| The Celerity open-source 511-core RISC-V tiered accelerator fabric: Fast architectures and design methodologies for fast chips S Davidson, S Xie, C Torng, K Al-Hawai, A Rovinski, T Ajayi, L Vega, ... IEEE Micro 38 (2), 30-41, 2018 | 134 | 2018 |
| Sparse-TPU: Adapting systolic arrays for sparse matrices X He, S Pal, A Amarnath, S Feng, DH Park, A Rovinski, H Ye, Y Chen, ... Proceedings of the 34th ACM international conference on supercomputing, 1-12, 2020 | 98 | 2020 |
| Celerity: An open source RISC-V tiered accelerator fabric T Ajayi, K Al-Hawaj, A Amarnath, S Dai, S Davidson, P Gao, G Liu, A Lotfi, ... Symp. on High Performance Chips (Hot Chips), 2017 | 38 | 2017 |
| A 1.4 GHz 695 Giga Risc-V inst/s 496-core manycore processor with mesh on-chip network and an all-digital synthesized PLL in 16nm CMOS A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ... 2019 Symposium on VLSI Circuits, C30-C31, 2019 | 35 | 2019 |
| A 7.3 m output non-zeros/j, 11.7 m output non-zeros/gb reconfigurable sparse matrix–matrix multiplication accelerator DH Park, S Pal, S Feng, P Gao, J Tan, A Rovinski, S Xie, C Zhao, ... IEEE Journal of Solid-State Circuits 55 (4), 933-944, 2020 | 34 | 2020 |
| Evaluating celerity: A 16-nm 695 Giga-RISC-V instructions/s manycore processor with synthesizable PLL A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ... IEEE Solid-State Circuits Letters 2 (12), 289-292, 2019 | 33 | 2019 |
| Transmuter: Bridging the efficiency gap using memory and dataflow reconfiguration S Pal, S Feng, D Park, S Kim, A Amarnath, CS Yang, X He, J Beaumont, ... Proceedings of the ACM International Conference on Parallel Architectures …, 2020 | 31 | 2020 |
| A 7.3 m output non-zeros/j sparse matrix-matrix multiplication accelerator using memory reconfiguration in 40 nm S Pal, D Park, S Feng, P Gao, J Tan, A Rovinski, S Xie, C Zhao, ... 2019 Symposium on VLSI Technology, C150-C151, 2019 | 27 | 2019 |
| SparseAdapt: Runtime control for sparse linear algebra on a reconfigurable accelerator S Pal, A Amarnath, S Feng, M O'Boyle, R Dreslinski, C Dubach MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 20 | 2021 |
| STOMP: A tool for evaluation of scheduling policies in heterogeneous multi-processors A Vega, A Amarnath, JD Wellman, H Kassa, S Pal, H Franke, ... arXiv preprint arXiv:2007.14371, 2020 | 16 | 2020 |
| Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm T Ajayi, K Al-Hawaj, A Amarnath, S Dai, S Davidson, P Gao, G Liu, A Rao, ... First Workshop on Computer Architecture Research with RISC-V (CARRV 2017), 2017 | 16 | 2017 |
| A survey describing beyond Si transistors and exploring their implications for future processors H Kim, A Amarnath, J Bagherzadeh, N Talati, RG Dreslinski ACM Journal on Emerging Technologies in Computing Systems (JETC) 17 (3), 1-44, 2021 | 14 | 2021 |
| Heterogeneity-aware scheduling on SoCs for autonomous vehicles A Amarnath, S Pal, HT Kassa, A Vega, A Buyuktosunoglu, H Franke, ... IEEE Computer Architecture Letters 20 (2), 82-85, 2021 | 14 | 2021 |
| 3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology A Amarnath, J Bagherzadeh, J Tan, RG Dreslinski 2019 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2019 | 10 | 2019 |
| A carbon nanotube transistor based RISC-V processor using pass transistor logic A Amarnath, S Feng, S Pal, T Ajayi, A Rovinski, RG Dreslinski 2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017 | 8 | 2017 |
| 14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration MC Dos Santos, T Jia, J Zuckerman, M Cochet, D Giri, EJ Loscalzo, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 262-264, 2024 | 7* | 2024 |
| STOMP: Agile evaluation of scheduling policies in heterogeneous multi-processors A Vega, JD Wellman, H Franke, A Buyuktosunoglu, P Bose, A Amarnath, ... DOSSA-3 Workshop@ HPCA, 2021 | 7 | 2021 |
| Hetsched: Quality-of-mission aware scheduling for autonomous vehicle socs A Amarnath, S Pal, H Kassa, A Vega, A Buyuktosunoglu, H Franke, ... arXiv preprint arXiv:2203.13396, 2022 | 5 | 2022 |
| Unlocking real-time fluorescence lifetime imaging: multi-pixel parallelism for FPGA-accelerated processing I Erbas, A Amarnath, V Pandey, K Swaminathan, N Wang, X Intes arXiv preprint arXiv:2410.07364, 2024 | 3 | 2024 |
Ronald DreslinskiUniversity of MichiganZweryfikowany adres z umich.edu