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Mathias Soeken
Mathias Soeken
Microsoft
Zweryfikowany adres z epfl.ch - Strona główna
Tytuł
Cytowane przez
Cytowane przez
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Verifying UML/OCL models using Boolean satisfiability
M Soeken, R Wille, M Kuhlmann, M Gogolla, R Drechsler
Proceedings of the Conference on Design, Automation and Test in Europe, 1341 …, 2010
1852010
Assessing requirements to scale to practical quantum advantage
ME Beverland, P Murali, M Troyer, KM Svore, T Hoeffler, V Kliuchnikov, ...
arXiv preprint arXiv:2211.07629, 2022
1602022
Assisted behavior driven development using natural language processing
M Soeken, R Wille, R Drechsler
International Conference on Modelling Techniques and Tools for Computer …, 2012
1402012
RevKit: A Toolkit for Reversible Circuit Design.
M Soeken, S Frehse, R Wille, R Drechsler
Multiple-Valued Logic and Soft Computing 18 (1), 55-65, 2012
1382012
Synthesis of reversible circuits with minimal lines for large functions
M Soeken, R Wille, C Hilken, N Przigoda, R Drechsler
Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific, 85-92, 2012
1372012
The EPFL logic synthesis libraries
M Soeken, H Riener, W Haaswijk, E Testa, B Schmitt, G Meuli, F Mozafari, ...
arXiv preprint arXiv:1805.05121, 2018
1332018
Quantum programming languages
B Heim, M Soeken, S Marshall, C Granade, M Roetteler, A Geller, ...
Nature Reviews Physics 2 (12), 709-722, 2020
1152020
Exact synthesis of majority-inverter graphs and its applications
M Soeken, L Amaru, PE Gaillardon, G De Micheli
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017
1132017
Deep Learning for Logic Optimization Algorithms
WJ Haaswijk, E Collins, BLA Seguin, M Soeken, S Süsstrunk, F Kaplan, ...
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2018
1122018
Formal Verification of Integer Multipliers by Combining Grobner Basis with Logic Reduction
A Sayed-Ahmed, D Große, U Kühne, M Soeken, R Drechsler
103*
Improved quantum circuits for elliptic curve discrete logarithms
T Häner, S Jaques, M Naehrig, M Roetteler, M Soeken
International Conference on Post-Quantum Cryptography, 425-444, 2020
1002020
RevKit: an open source toolkit for the design of reversible circuits
M Soeken, S Frehse, R Wille, R Drechsler
International Workshop on Reversible Computation, 64-76, 2011
982011
Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs
S Shirinzadeh, M Soeken, PE Gaillardon, R Drechsler
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 948-953, 2016
912016
A Novel Basis for Logic Rewriting
W Haaswijk, M Soeken, L Amaru, PE Gaillardon, G De Micheli
Proceedings of the 22nd Asia and South Pacific Design Automation Conference …, 2017
822017
Verifying dynamic aspects of UML models.
M Soeken, R Wille, R Drechsler
DATE, 1077-1082, 2011
812011
Approximation-aware Rewriting of AIGs for Error Tolerant Applications
A Chandrasekharan, M Soeken, D Große, R Drechsler
81*
Reducing the number of lines in reversible circuits
R Wille, M Soeken, R Drechsler
Design Automation Conference (DAC), 2010 47th ACM/IEEE, 647-652, 2010
802010
On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis
H Riener, W Haaswijk, A Mishchenko, G De Micheli, M Soeken
76*
BDD Minimization for Approximate Computing
M Soeken, D Große, A Chandrasekharan, R Drechsler
73*
Improving the mapping of reversible circuits to quantum circuits using multiple target lines
R Wille, M Soeken, C Otterstedt, R Drechsler
Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific …, 2013
702013
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