16.2 A 0.19 pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS SK Mathew, SK Satpathy, MA Anders, H Kaul, SK Hsu, A Agarwal, ...
2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014
271 2014 2.4 Gbps, 7 mW all-digital PVT-variation tolerant true random number generator for 45 nm CMOS high-performance microprocessors SK Mathew, S Srinivasan, MA Anders, H Kaul, SK Hsu, F Sheikh, ...
IEEE Journal of Solid-State Circuits 47 (11), 2807-2821, 2012
216 2012 Catnap: Energy proportional multiple network-on-chip R Das, S Narayanasamy, SK Satpathy, RG Dreslinski
Proceedings of the 40th annual international symposium on Computer …, 2013
205 2013 340 mv–1.1 v, 289 gbps/w, 2090-gate nanoaes hardware accelerator with area-optimized encrypt/decrypt gf (2 4) 2 polynomials in 22 nm tri-gate cmos S Mathew, S Satpathy, V Suresh, M Anders, H Kaul, A Agarwal, S Hsu, ...
IEEE Journal of Solid-State Circuits 50 (4), 1048-1058, 2015
168 2015 SK Mathew, D Johnston, S Satpathy, V Suresh, P Newman, MA Anders, ...
IEEE Journal of Solid-State Circuits 51 (7), 1695-1704, 2016
134 2016 Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores D Fick, RG Dreslinski, B Giridhar, G Kim, S Seo, M Fojtik, S Satpathy, ...
2012 IEEE International Solid-State Circuits Conference, 190-192, 2012
121 2012 A 4-fJ/b delay-hardened physically unclonable function circuit with selective bit destabilization in 14-nm trigate CMOS S Satpathy, SK Mathew, V Suresh, MA Anders, H Kaul, A Agarwal, ...
IEEE Journal of Solid-State Circuits 52 (4), 940-949, 2017
120 2017 Swizzle-switch networks for many-core systems K Sewell, RG Dreslinski, T Manville, S Satpathy, N Pinckney, G Blake, ...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2 (2 …, 2012
112 2012 An all-digital unified physically unclonable function and true random number generator featuring self-calibrating hierarchical Von Neumann extraction in 14-nm tri-gate CMOS SK Satpathy, SK Mathew, R Kumar, V Suresh, MA Anders, H Kaul, ...
IEEE Journal of Solid-State Circuits 54 (4), 1074-1085, 2019
95 2019 A 340 mV-to-0.9 V 20.2 Tb/s source-synchronous hybrid packet/circuit-switched 16× 16 network-on-chip in 22 nm tri-gate CMOS G Chen, MA Anders, H Kaul, SK Satpathy, SK Mathew, SK Hsu, ...
IEEE Journal of Solid-State Circuits 50 (1), 59-67, 2014
88 2014 Centip3De: A cluster-based NTC architecture with 64 ARM Cortex-M3 cores in 3D stacked 130 nm CMOS D Fick, RG Dreslinski, B Giridhar, G Kim, S Seo, M Fojtik, S Satpathy, ...
IEEE Journal of Solid-State Circuits 48 (1), 104-117, 2012
63 2012 Centip3de: A 64-core, 3d stacked near-threshold system RG Dreslinski, D Fick, B Giridhar, G Kim, S Seo, M Fojtik, S Satpathy, ...
IEEE Micro 33 (2), 8-16, 2013
58 2013 Techniques for secure message authentication with unified hardware acceleration VB Suresh, KS Yap, SK Mathew, SK Satpathy
US Patent App. 15/393,196, 2018
39 2018 13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS S Satpathy, S Mathew, J Li, P Koeberl, M Anders, H Kaul, G Chen, ...
ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), 239-242, 2014
38 2014 A 4.5 Tb/s 3.4 Tb/s/W 64× 64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS S Satpathy, K Sewell, T Manville, YP Chen, R Dreslinski, D Sylvester, ...
2012 IEEE International Solid-State Circuits Conference, 478-480, 2012
37 2012 2.9 tops/w reconfigurable dense/sparse matrix-multiply accelerator with unified int8/inti6/fp16 datapath in 14nm tri-gate cmos M Anders, H Kaul, S Mathew, V Suresh, S Satpathy, A Agarwal, S Hsu, ...
2018 IEEE Symposium on VLSI Circuits, 39-40, 2018
36 2018 Method, apparatus and system for a source-synchronous circuit-switched network on a chip (NOC) GK Chen, MA Anders, H Kaul, SK Satpathy, RK Krishnamurthy
US Patent 9,652,425, 2017
34 2017 Apparatuses and methods for frequency scaling a message scheduler data path of a hashing accelerator V Suresh, S Mathew, S Satpathy
US Patent 10,928,847, 2021
33 2021 Energy-efficient bitcoin mining hardware accelerators VB Suresh, SK Satpathy, SK Mathew
US Patent 10,313,108, 2019
30 2019 Using dark bits to reduce physical unclonable function (PUF) error rate without storing dark bits location SK Mathew, SK Satpathy, P Koeberl, J Li, RK Krishnamurthy, A Rajan
US Patent 9,262,256, 2016
30 2016