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Yuval Yarom
Yuval Yarom
Ruhr University Bochum
Zweryfikowany adres z rub.de - Strona główna
Tytuł
Cytowane przez
Cytowane przez
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Spectre attacks: Exploiting speculative execution
P Kocher, J Horn, A Fogh, D Genkin, D Gruss, W Haas, M Hamburg, ...
IEEE Symposium on Security and Privacy, 2019
33742019
Meltdown: Reading Kernel Memory from User Space
M Lipp, M Schwarz, D Gruss, T Prescher, W Haas, A Fogh, J Horn, ...
USENIX Security Symposium, 973-990, 2018
2797*2018
Flush+Reload: a High Resolution, Low Noise, L3 Cache Side-Channel Attack.
Y Yarom, KE Falkner
USENIX Security Symposium, 719-732, 2014
21392014
Last-Level Cache Side-Channel Attacks are Practical
F Liu, Y Yarom, Q Ge, G Heiser, RB Lee
IEEE Symposium on Security and Privacy (S&P), 2015
14762015
Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution
J Van Bulck, M Minkin, O Weisse, D Genkin, B Kasikci, F Piessens, ...
USENIX Security Symposium, 991-1008, 2018
14712018
A Survey of Microarchitectural Timing Attacks and Countermeasures on Contemporary Hardware
Q Ge, Y Yarom, D Cock, G Heiser
Journal of Cryptographic Engineering 8 (1), 1-27, 2018
5372018
CATalyst: Defeating Last-Level Cache Side Channel Attacks in Cloud Computing
F Liu, Q Ge, Y Yarom, F Mckeen, C Rozas, G Heiser, RB Lee
22nd IEEE Symposium on High Performance Computer Architecture (HPCA 2016), 2016
5372016
Fallout: Leaking Data on Meltdown-resistant CPUs
C Canella, D Genkin, L Giner, D Gruss, M Lipp, M Minkin, D Moghimi, ...
CCS, 2019
444*2019
CacheBleed: A timing attack on OpenSSL constant time RSA
Y Yarom, D Genkin, N Heninger
Journal of Cryptographic Engineering 7 (2), 99-112, 2017
4232017
LVI: Hijacking Transient Execution through Microarchitectural Load Value Injection
J Van Bulck, D Moghimi, M Schwarz, M Lipp, M Minkin, D Genkin, ...
IEEE SP 2020, 2020
3622020
Another flip in the wall of Rowhammer defenses
D Gruss, M Lipp, M Schwarz, D Genkin, J Juffinger, S O'Connell, ...
IEEE Symposium on Security and Privacy (S&P), 2018
3222018
“Ooh Aah... Just a Little Bit”: A small amount of side channel can go a long way
N Benger, J van de Pol, NP Smart, Y Yarom
Cryptographic Hardware and Embedded Systems (CHES 2014), 75-92, 2014
2782014
Flush, Gauss, and reload–a cache attack on the BLISS lattice-based signature scheme
L Groot Bruinderink, A Hülsing, T Lange, Y Yarom
Cryptographic Hardware and Embedded Systems (CHES 2016), 2016
2752016
Foreshadow-NG: Breaking the virtual memory abstraction with transient out-of-order execution
O Weisse, J Van Bulck, M Minkin, D Genkin, B Kasikci, F Piessens, ...
Preprint, 2018
2632018
Recovering OpenSSL ECDSA Nonces Using the FLUSH+RELOAD Cache Side-channel Attack.
Y Yarom, N Benger
IACR Cryptology ePrint Archive 2014/140, 2014
2592014
ECDSA key extraction from mobile devices via nonintrusive physical side channels
D Genkin, L Pachmanov, I Pipman, E Tromer, Y Yarom
23rd ACM Conference on Computer and Communications Security (CCS 2016), 2016
2482016
RAMBleed: Reading Bits in Memory Without Accessing Them
A Kwong, D Genkin, D Gruss, Y Yarom
IEEE SP, 2020
2462020
CacheOut: Leaking data on Intel CPUs via cache evictions
S van Schaik, M Minkin, A Kwong, D Genkin, Y Yarom
IEEE SP, 2021
2002021
Website Fingerprinting Through the Cache Occupancy Channel and its Real World Practicality
A Shusterman, Z Avraham, E Croitoru, Y Haskal, L Kang, D Levi, ...
IEEE Transactions on Dependable and Secure Computing, 2020
1942020
Mapping the Intel Last-Level Cache
Y Yarom, Q Ge, F Liu, RB Lee, G Heiser
IACR Cryptology ePrint Archive 2015-905, 2015
1462015
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