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Joel Emer
Joel Emer
Professor of the Practice, MIT - Sr. Distinguished Research Scientist, Nvidia
Zweryfikowany adres z csail.mit.edu - Strona główna
Tytuł
Cytowane przez
Cytowane przez
Rok
Efficient processing of deep neural networks: A tutorial and survey
V Sze, YH Chen, TJ Yang, JS Emer
Proceedings of the IEEE 105 (12), 2295-2329, 2017
46252017
Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks
YH Chen, T Krishna, JS Emer, V Sze
IEEE journal of solid-state circuits 52 (1), 127-138, 2016
40622016
Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks
YH Chen, J Emer, V Sze
ACM SIGARCH computer architecture news 44 (3), 367-379, 2016
20092016
SCNN: An accelerator for compressed-sparse convolutional neural networks
A Parashar, M Rhu, A Mukkara, A Puglielli, R Venkatesan, B Khailany, ...
ACM SIGARCH computer architecture news 45 (2), 27-40, 2017
15192017
A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor
SS Mukherjee, C Weaver, J Emer, SK Reinhardt, T Austin
Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003
13292003
Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor
DM Tullsen, SJ Eggers, JS Emer, HM Levy, JL Lo, RL Stamm
Proceedings of the 23rd annual international symposium on Computer …, 1996
12351996
Eyeriss v2: A flexible accelerator for emerging deep neural networks on mobile devices
YH Chen, TJ Yang, J Emer, V Sze
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 9 (2 …, 2019
11102019
High performance cache replacement using re-reference interval prediction (RRIP)
A Jaleel, KB Theobald, SC Steely Jr, J Emer
ACM SIGARCH computer architecture news 38 (3), 60-71, 2010
10292010
Adaptive insertion policies for high performance caching
MK Qureshi, A Jaleel, YN Patt, SC Steely, J Emer
ACM SIGARCH Computer Architecture News 35 (2), 381-391, 2007
9922007
Simultaneous multithreading: A platform for next-generation processors
SJ Eggers, JS Emer, HM Levy, JL Lo, RL Stamm, DM Tullsen
IEEE micro 17 (5), 12-19, 1997
7191997
Understanding error propagation in deep learning neural network (DNN) accelerators and applications
G Li, SKS Hari, M Sullivan, T Tsai, K Pattabiraman, J Emer, SW Keckler
Proceedings of the International Conference for High Performance Computing …, 2017
6432017
The soft error problem: An architectural perspective
SS Mukherjee, J Emer, SK Reinhardt
11th International Symposium on High-Performance Computer Architecture, 243-247, 2005
6132005
There’s plenty of room at the Top: What will drive computer performance after Moore’s law?
CE Leiserson, NC Thompson, JS Emer, BC Kuszmaul, BW Lampson, ...
Science 368 (6495), eaam9744, 2020
5072020
Memory dependence prediction using store sets
GZ Chrysos, JS Emer
ACM SIGARCH Computer Architecture News 26 (3), 142-153, 1998
4891998
Timeloop: A systematic approach to dnn accelerator evaluation
A Parashar, P Raina, YS Shao, YH Chen, VA Ying, A Mukkara, ...
2019 IEEE international symposium on performance analysis of systems and …, 2019
4872019
Hardware for machine learning: Challenges and opportunities
V Sze, YH Chen, J Emer, A Suleiman, Z Zhang
2017 IEEE custom integrated circuits conference (CICC), 1-8, 2017
4842017
Simba: Scaling deep-learning inference with multi-chip-module-based architecture
YS Shao, J Clemons, R Venkatesan, B Zimmer, M Fojtik, N Jiang, B Keller, ...
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
4702019
Scheduling heterogeneous multi-cores through performance impact estimation (PIE)
K Van Craeynest, A Jaleel, L Eeckhout, P Narvaez, J Emer
ACM SIGARCH Computer Architecture News 40 (3), 213-224, 2012
4552012
Adaptive insertion policies for managing shared caches
A Jaleel, W Hasenplaugh, M Qureshi, J Sebot, S Steely Jr, J Emer
Proceedings of the 17th international conference on Parallel architectures …, 2008
4232008
Sparse convolutional neural network accelerator
WJ Dally, A Parashar, JS Emer, SW Keckler, LR Dennison
US Patent 10,891,538, 2021
4122021
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