| Edgebert: Sentence-level energy optimizations for latency-aware multi-task nlp inference T Tambe, C Hooper, L Pentecost, T Jia, EY Yang, M Donato, V Sanh, ... MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture …, 2021 | 120 | 2021 |
| Analyzing and improving fault tolerance of learning-based navigation systems Z Wan, A Anwar, YS Hsiao, T Jia, VJ Reddi, A Raychowdhury 2021 58th ACM/IEEE Design Automation Conference (DAC), 841-846, 2021 | 31 | 2021 |
| 7.8 A 22nm delta-sigma computing-in-memory (Δ∑ CIM) SRAM macro with near-zero-mean outputs and LSB-first ADCs achieving 21.38 TOPS/W for 8b-MAC edge AI processing P Chen, M Wu, W Zhao, J Cui, Z Wang, Y Zhang, Q Wang, J Ru, L Shen, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 140-142, 2023 | 28 | 2023 |
| Mavfi: An end-to-end fault analysis framework with anomaly detection and recovery for micro aerial vehicles YS Hsiao, Z Wan, T Jia, R Ghosal, A Mahmoud, A Raychowdhury, ... 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 27 | 2023 |
| A 12nm agile-designed SoC for swarm-based perception with heterogeneous IP blocks, a reconfigurable memory hierarchy, and an 800MHz multi-plane NoC T Jia, P Mantovani, MC Dos Santos, D Giri, J Zuckerman, EJ Loscalzo, ... ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC …, 2022 | 25 | 2022 |
| A 22nm Delta-Sigma Computing-In-Memory (Δ∑ CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38 TOPS/W for 8b-MAC Edge AI Processing. P Chen, M Wu, W Zhao, J Cui, Z Wang, Y Zhang, Q Wang, J Ru, L Shen, ... ISSCC, 140-141, 2023 | 23 | 2023 |
| 22.9 A 12nm 18.1 TFLOPs/W sparse transformer processor with entropy-based early exit, mixed-precision predication and fine-grained power management T Tambe, J Zhang, C Hooper, T Jia, PN Whatmough, J Zuckerman, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 342-344, 2023 | 21 | 2023 |
| Ncpu: An embedded neural cpu architecture on resource-constrained low power devices for real-time end-to-end performance T Jia, Y Ju, R Joseph, J Gu 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture …, 2020 | 19 | 2020 |
| A dynamic timing enhanced DNN accelerator with compute-adaptive elastic clock chain technique T Jia, Y Ju, J Gu IEEE Journal of Solid-State Circuits 56 (1), 55-65, 2020 | 18 | 2020 |
| An instruction-driven adaptive clock management through dynamic phase scaling and compiler assistance for a low power microprocessor T Jia, R Joseph, J Gu IEEE Journal of Solid-State Circuits 54 (8), 2327-2338, 2019 | 18 | 2019 |
| A fully integrated buck regulator with 2-GHz resonant switching for low-power applications T Jia, J Gu IEEE Journal of Solid-State Circuits 53 (9), 2663-2674, 2018 | 17 | 2018 |
| Frl-fi: Transient fault analysis for federated reinforcement learning-based navigation systems Z Wan, A Anwar, A Mahmoud, T Jia, YS Hsiao, VJ Reddi, ... 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 430-435, 2022 | 16 | 2022 |
| 31.3 A compute-adaptive elastic clock-chain technique with dynamic timing enhancement for 2D PE-array-based accelerators T Jia, Y Ju, J Gu 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 482-484, 2020 | 15 | 2020 |
| A compact stacked bidirectional antenna for dual-polarized WLAN applications T Jia, X Li Progress In Electromagnetics Research C 44, 95-108, 2013 | 15 | 2013 |
| Compiler-guided instruction-level clock scheduling for timing speculative processors Y Fan, T Jia, J Gu, S Campanoni, R Joseph Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 13 | 2018 |
| Omu: A probabilistic 3d occupancy mapping accelerator for real-time octomap at the edge T Jia, EY Yang, YS Hsiao, J Cruz, D Brooks, GY Wei, VJ Reddi arXiv preprint arXiv:2205.03325, 2022 | 12 | 2022 |
| An instruction driven adaptive clock phase scaling with timing encoding and online instruction calibration for a low power microprocessor T Jia, R Joseph, J Gu ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC), 94-97, 2018 | 12 | 2018 |
| A scalable methodology for agile chip development with open-source hardware components MC Santos, T Jia, M Cochet, K Swaminathan, J Zuckerman, P Mantovani, ... Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022 | 10 | 2022 |
| Supply voltage decoupling circuits for voltage droop mitigation X Zhang, T Takken, T Jia US Patent 10,972,083, 2021 | 10 | 2021 |
| An adaptive clock management scheme exploiting instruction-based dynamic timing slack for a general-purpose graphics processor unit with deep pipeline and out-of-order execution T Jia, R Joseph, J Gu International Solid-State Circuit Conference, 2019 | 10 | 2019 |
Jie GuProfessor of Electrical Engineering and Computer Science, Northwestern UniversityZweryfikowany adres z northwestern.edu
