Ge0. 97Sn0. 03 p-channel metal-oxide-semiconductor field-effect transistors: Impact of Si surface passivation layer thickness and post metal annealing P Guo, G Han, X Gong, B Liu, Y Yang, W Wang, Q Zhou, J Pan, Z Zhang, ...
Journal of Applied Physics 114 (4), 2013
55 2013 22-nm FD-SOI embedded MRAM technology for low-power automotive-grade-l MCU applications K Lee, R Chao, K Yamane, VB Naik, H Yang, J Kwon, NL Chung, ...
2018 IEEE International Electron Devices Meeting (IEDM), 27.1. 1-27.1. 4, 2018
45 2018 Selenium segregation for effective Schottky barrier height reduction in NiGe/n–Ge contacts Y Tong, B Liu, PSY Lim, YC Yeo
IEEE electron device letters 33 (6), 773-775, 2012
44 2012 Toward conformal damage-free doping with abrupt ultrashallow junction: Formation of Si monolayers and laser anneal as a novel doping technique for InGaAs nMOSFETs EYJ Kong, P Guo, X Gong, B Liu, YC Yeo
IEEE Transactions on Electron Devices 61 (4), 1039-1046, 2014
35 2014 Ohmic Contact Formation on N-Type Using Selenium or Sulfur Implant and SegregationY Tong, G Han, B Liu, Y Yang, L Wang, W Wang, YC Yeo
IEEE transactions on electron devices 60 (2), 746-752, 2013
34 2013 22-nm FD-SOI embedded MRAM with full solder reflow compatibility and enhanced magnetic immunity K Lee, K Yamane, S Noh, VB Naik, H Yang, SH Jang, J Kwon, ...
2018 IEEE Symposium on VLSI Technology, 183-184, 2018
33 2018 Methods for manufacturing semiconductor devices having different threshold voltages B Liu, S Kim
US Patent 9,514,990, 2016
32 2016 Towards high performance Ge1−x Snx and In0.7 Ga0.3 As CMOS: A novel common gate stack featuring sub-400 °C Si2 H6 passivation, single TaN metal gate … X Gong, S Su, B Liu, L Wang, W Wang, Y Yang, E Kong, B Cheng, G Han, ...
2012 Symposium on VLSI Technology (VLSIT), 99-100, 2012
32 2012 Sub-400 °C Si2 H6 Passivation, HfO2 Gate Dielectric, and Single TaN Metal Gate: A Common Gate Stack Technology for In0.7 Ga0.3 As and Ge1-x Snx CMOS X Gong, G Han, B Liu, L Wang, W Wang, Y Yang, EYJ Kong, S Su, C Xue, ...
IEEE transactions on electron devices 60 (5), 1640-1648, 2013
30 2013 Germanium–Tin Junction Formed Using Phosphorus Ion Implant and 400 Rapid Thermal Anneal L Wang, S Su, W Wang, Y Yang, Y Tong, B Liu, P Guo, X Gong, G Zhang, ...
IEEE electron device letters 33 (11), 1529-1531, 2012
26 2012 Gate stack reliability of MOSFETs with high-mobility channel materials: Bias temperature instability X Gong, B Liu, YC Yeo
IEEE Transactions on Device and Materials Reliability 13 (4), 524-533, 2013
25 2013 An efficient binary integer programming model for residency time-constrained cluster tools with chamber cleaning requirements Y Qiao, Y Lu, J Li, S Zhang, N Wu, B Liu
IEEE Transactions on Automation Science and Engineering 19 (3), 1757-1771, 2021
24 2021 Low-power and high-sensitivity system-on-chip hall effect sensor B Liu, Y Sun, Y Ding, P Cao, A Liu, SY Ong, M Tiong, G Cheng, MN Islam, ...
2017 IEEE SENSORS, 1-3, 2017
22 2017 High-Performance Germanium -Gate MuGFET With Schottky-Barrier Nickel Germanide Source/Drain and Low-Temperature Disilane-Passivated Gate Stack B Liu, X Gong, G Han, PSY Lim, Y Tong, Q Zhou, Y Yang, N Daval, ...
IEEE electron device letters 33 (10), 1336-1338, 2012
22 2012 Germanium multiple-gate field-effect transistors formed on germanium-on-insulator substrate B Liu, X Gong, C Zhan, G Han, HC Chin, ML Ling, J Li, Y Liu, J Hu, ...
IEEE transactions on electron devices 60 (6), 1852-1860, 2013
20 2013 Contact-resistance reduction for strained n-FinFETs with silicon–carbon source/drain and platinum-based silicide contacts featuring tellurium implantation and segregation SM Koh, EYJ Kong, B Liu, CM Ng, GS Samudra, YC Yeo
IEEE transactions on electron devices 58 (11), 3852-3862, 2011
20 2011 High performance Ge CMOS with novel InAlP-passivated channels for future sub-10 nm technology node applications B Liu, X Gong, R Cheng, P Guo, Q Zhou, MHS Owen, C Guo, L Wang, ...
2013 IEEE International Electron Devices Meeting, 26.7. 1-26.7. 3, 2013
18 2013 Germanium multiple-gate field-effect transistor with in situ boron-doped raised source/drain B Liu, C Zhan, Y Yang, R Cheng, P Guo, Q Zhou, EYJ Kong, N Daval, ...
IEEE transactions on electron devices 60 (7), 2135-2141, 2013
15 2013 Asymetrically strained high performance Germanium gate-all-around nanowire p-FETs featuring 3.5 nm wire width and contractible phase change liner stressor (Ge2Sb2Te5) R Cheng, B Liu, P Guo, Y Yang, Q Zhou, X Gong, Y Dong, Y Tong, ...
Electron Devices Meeting (IEDM), 2013 IEEE International, 26.6. 1-26.6. 4, 2013
14 2013 A new liner stressor (GeTe) featuring stress enhancement due to very large phase-change induced volume contraction for p-channel FinFETs R Cheng, Y Ding, SM Koh, A Gyanathan, F Bai, B Liu, YC Yeo
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14 2012