| Interconnect-driven physical synthesis using persistent virtual routing P Saxena, V Khandelwal, C Qiao, PH Ho, JC Lin, MA Iyer US Patent 7,853,915, 2010 | 166 | 2010 |
| FIRE: A fault-independent combinational redundancy identification algorithm MA Iyer, M Abramovici IEEE transactions on very large scale integration (VLSI) systems 4 (2), 295-301, 1996 | 123 | 1996 |
| Identifying sequential redundancies without search MA Iyer, DE Long, M Abramovici Proceedings of the 33rd annual Design Automation Conference, 457-462, 1996 | 102 | 1996 |
| High-definition routing congestion prediction for large-scale FPGAs MB Alawieh, W Li, Y Lin, L Singhal, MA Iyer, DZ Pan 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 26-31, 2020 | 80 | 2020 |
| RACE: A word-level ATPG-based constraints solver system for smart random simulation MA Iyer International Test Conference, 2003. Proceedings. ITC 2003., 299-299, 2003 | 61 | 2003 |
| Low-cost redundancy identification for combinational circuits MA Iyer, M Abramovici Proceedings of 7th International Conference on VLSI Design, 315-318, 1994 | 60 | 1994 |
| One-pass redundancy identification and removal M Abramovici, MA Iyer Proceedings International Test Conference 1992, 807-807, 1992 | 58 | 1992 |
| Identifying sequentially untestable faults using illegal states DE Long, MA Iyer, M Abramovici Proceedings 13th IEEE VLSI Test Symposium, 4-11, 1995 | 54 | 1995 |
| Sequentially untestable faults identified without search (" simple implications beat exhaustive search!") MA Iyer, M Abramovici Proceedings., International Test Conference, 259-266, 1995 | 51 | 1995 |
| Wavefront technology mapping L Stok, MA Iyer, AJ Sullivan Proceedings of the conference on Design, automation and test in Europe, 108-es, 1999 | 47 | 1999 |
| FILL and FUNI: Algorithms to identify illegal states and sequentially untestable faults DE Long, MA Iyer, M Abramovici ACM Transactions on Design Automation of Electronic Systems (TODAES) 5 (3 …, 2000 | 39 | 2000 |
| Method and apparatus for automatic orientation optimization A Arunachalam, MA Iyer US Patent 7,937,682, 2011 | 35 | 2011 |
| Wavefront technology mapping MA Iyer, L Stok, AJ Sullivan US Patent 6,334,205, 2001 | 34 | 2001 |
| Energy minimization based delay testing ST Chakradhar, MA Iyer, VD Agrawal Proceedings The European Conference on Design Automation, 280,281,282,283 …, 1992 | 34 | 1992 |
| Method and apparatus for improving efficiency of constraint solving MA Iyer US Patent 7,302,417, 2007 | 27 | 2007 |
| Agilex™ generation of intel® fpgas IK Ganusov, MA Iyer, N Cheng, A Meisler 2020 IEEE Hot Chips 32 Symposium (HCS), 1-26, 2020 | 26 | 2020 |
| Energy models for delay testing ST Chakradhar, MA Iyer, VD Agrawal IEEE transactions on computer-aided design of integrated circuits and …, 1995 | 26 | 1995 |
| DREAMPlaceFPGA: An open-source analytical placer for large scale heterogeneous FPGAs using deep-learning toolkit RS Rajarathnam, MB Alawieh, Z Jiang, M Iyer, DZ Pan 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 300-306, 2022 | 21 | 2022 |
| Construction of a technology library for use in an electronic design automation system that converts the technology library into non-linear, gain-based models for estimating … M Iyer, A Kapoor US Patent 6,789,232, 2004 | 21 | 2004 |
| A robust solution to the timing convergence problem in high-performance design N Shenoy, M Iyer, R Damiano, K Harer, HK Ma, P Thilking Proceedings 1999 IEEE International Conference on Computer Design: VLSI in …, 1999 | 21 | 1999 |