| Ultra-low power VLSI circuit design demystified and explained: A tutorial M Alioto IEEE Transactions on Circuits and Systems I: Regular Papers 59 (1), 3-29, 2012 | 524 | 2012 |
| Enabling the internet of things M Alioto Cham: Springer International Publishing, 2017 | 352 | 2017 |
| Analysis and comparison on full adder block in submicron technology M Alioto, G Palumbo IEEE transactions on very large scale integration (VLSI) systems 10 (6), 806-823, 2002 | 312 | 2002 |
| Understanding the effect of process variations on the delay of static and domino logic M Alioto, G Palumbo, M Pennisi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (5), 697-710, 2009 | 233 | 2009 |
| Understanding DC behavior of subthreshold CMOS logic through closed-form analysis M Alioto IEEE Transactions on Circuits and Systems I: Regular Papers 57 (7), 1597-1607, 2010 | 228 | 2010 |
| Model and design of bipolar and MOS current-mode logic: CML, ECL and SCL digital circuits M Alioto, G Palumbo Springer Science & Business Media, 2005 | 201 | 2005 |
| Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: Part I—Methodology and design strategies M Alioto, E Consoli, G Palumbo IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (5), 725-736, 2010 | 177* | 2010 |
| Leakage power analysis attacks: A novel class of attacks to nanometer cryptographic circuits M Alioto, L Giancane, G Scotti, A Trifiletti IEEE Transactions on Circuits and Systems I: Regular Papers 57 (2), 355-367, 2009 | 157 | 2009 |
| Design strategies for source coupled logic gates M Alioto, G Palumbo IEEE Transactions on Circuits and Systems I: Fundamental Theory and …, 2003 | 132 | 2003 |
| General strategies to design nanometer flip-flops in the energy-delay space M Alioto, E Consoli, G Palumbo IEEE Transactions on Circuits and Systems I: Regular Papers 57 (7), 1583-1596, 2009 | 127 | 2009 |
| 14.3 15fJ/b static physically unclonable functions for secure chip identification with< 2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm A Alvarez, W Zhao, M Alioto 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 113 | 2015 |
| Mixed full adder topologies for high-performance low-power arithmetic circuits M Alioto, G Di Cataldo, G Palumbo Microelectronics Journal 38 (1), 130-139, 2007 | 109 | 2007 |
| Variations in nanometer CMOS flip-flops: Part I—Impact of process variations on timing M Alioto, E Consoli, G Palumbo IEEE Transactions on Circuits and Systems I: Regular Papers 62 (8), 2035-2043, 2015 | 107 | 2015 |
| Leakage–delay tradeoff in FinFET logic circuits: A comparative analysis with bulk technology M Agostinelli, M Alioto, D Esseni, L Selmi IEEE Transactions on very large scale integration (VLSI) systems 18 (2), 232-245, 2009 | 107 | 2009 |
| A feedback strategy to improve the entropy of a chaos-based random bit generator T Addabbo, M Alioto, A Fort, S Rocchi, V Vignoli IEEE Transactions on Circuits and Systems I: Regular Papers 53 (2), 326-337, 2006 | 106 | 2006 |
| Conditional push-pull pulsed latches with 726fJ· ps energy-delay product in 65nm CMOS E Consoli, M Alioto, G Palumbo, J Rabaey 2012 IEEE International Solid-State Circuits Conference, 482-484, 2012 | 104 | 2012 |
| A class of maximum-period nonlinear congruential generators derived from the Rényi chaotic map T Addabbo, M Alioto, A Fort, A Pasini, S Rocchi, V Vignoli IEEE Transactions on Circuits and Systems I: Regular Papers 54 (4), 816-828, 2007 | 98 | 2007 |
| Trends in hardware security: From basics to ASICs M Alioto IEEE Solid-State Circuits Magazine 11 (3), 56-74, 2019 | 97 | 2019 |
| Static physically unclonable functions for secure chip identification with 1.9–5.8% native bit instability at 0.6–1 V and 15 fJ/bit in 65 nm AB Alvarez, W Zhao, M Alioto IEEE Journal of Solid-State Circuits 51 (3), 763-775, 2016 | 97 | 2016 |
| Fully synthesizable PUF featuring hysteresis and temperature compensation for 3.2% native BER and 1.02 fJ/b in 40 nm S Taneja, AB Alvarez, M Alioto IEEE Journal of Solid-State Circuits 53 (10), 2828-2839, 2018 | 94 | 2018 |
Longyang LinAssistant Professor, Southern University of Science and TechnologyAdresă de e-mail confirmată pe sustech.edu.cn
