| End-to-end design of a PUF-based privacy preserving authentication protocol A Aysu, E Gulcan, D Moriyama, P Schaumont, M Yung Cryptographic Hardware and Embedded Systems--CHES 2015: 17th International …, 2015 | 147 | 2015 |
| Low-cost and area-efficient FPGA implementations of lattice-based cryptography A Aysu, C Patterson, P Schaumont 2013 IEEE international symposium on hardware-oriented security and trust …, 2013 | 128 | 2013 |
| Maskednet: The first hardware inference engine aiming power side-channel protection A Dubey, R Cammarota, A Aysu 2020 IEEE International Symposium on Hardware Oriented Security and Trust …, 2020 | 127* | 2020 |
| SIMON says: Break area records of block ciphers on FPGAs A Aysu, E Gulcan, P Schaumont IEEE Embedded Systems Letters 6 (2), 37-40, 2014 | 115 | 2014 |
| An extensive study of flexible design methods for the number theoretic transform AC Mert, E Karabulut, E Öztürk, E Savaş, A Aysu IEEE Transactions on Computers 71 (11), 2829-2843, 2020 | 91 | 2020 |
| Horizontal side-channel vulnerabilities of post-quantum key exchange protocols A Aysu, Y Tobah, M Tiwari, A Gerstlauer, M Orshansky 2018 IEEE international symposium on hardware oriented security and trust …, 2018 | 75 | 2018 |
| BoMaNet: Boolean masking of an entire neural network A Dubey, R Cammarota, A Aysu Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 67 | 2020 |
| A flexible and scalable NTT hardware: Applications from homomorphically encrypted deep learning to post-quantum cryptography AC Mert, E Karabulut, E Öztürk, E Savaş, M Becchi, A Aysu 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 346-351, 2020 | 61 | 2020 |
| Efficient hardware implementations of high throughput SHA-3 candidates keccak, luffa and blue midnight wish for single-and multi-message hashing A Akin, A Aysu, OC Ulusel, E Savaş Proceedings of the 3rd International Conference on Security of Information …, 2010 | 58 | 2010 |
| Binary Ring-LWE hardware with power side-channel countermeasures A Aysu, M Orshansky, M Tiwari 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018 | 55 | 2018 |
| Falcon down: Breaking falcon post-quantum signature scheme through side-channel attacks E Karabulut, A Aysu 2021 58th ACM/IEEE Design Automation Conference (DAC), 691-696, 2021 | 54 | 2021 |
| Digital fingerprints for low-cost platforms using MEMS sensors A Aysu, NF Ghalaty, Z Franklin, MP Yali, P Schaumont Proceedings of the Workshop on Embedded Systems Security, 1-6, 2013 | 53 | 2013 |
| A flexible and compact hardware architecture for the SIMON block cipher E Gulcan, A Aysu, P Schaumont International workshop on lightweight cryptography for security and Privacy …, 2014 | 44 | 2014 |
| RANTT: A RISC-V architecture extension for the number theoretic transform E Karabulut, A Aysu 2020 30th International Conference on Field-Programmable Logic and …, 2020 | 43 | 2020 |
| An efficient non-profiled side-channel attack on the CRYSTALS-Dilithium post-quantum signature Z Chen, E Karabulut, A Aysu, Y Ma, J Jing 2021 IEEE 39th International Conference on Computer Design (ICCD), 583-590, 2021 | 39 | 2021 |
| Guarding machine learning hardware against physical side-channel attacks A Dubey, R Cammarota, V Suresh, A Aysu ACM Journal on Emerging Technologies in Computing Systems (JETC) 18 (3), 1-31, 2022 | 37 | 2022 |
| Single-trace side-channel attacks on ω-small polynomial sampling: With applications to ntru, NTRU prime, and CRYSTALS-DILITHIUM E Karabulut, E Alkim, A Aysu 2021 IEEE International Symposium on Hardware Oriented Security and Trust …, 2021 | 37 | 2021 |
| Modulonet: Neural networks meet modular arithmetic for efficient hardware masking A Dubey, A Ahmad, MA Pasha, R Cammarota, A Aysu IACR Transactions on Cryptographic Hardware and Embedded Systems, 506-556, 2022 | 36 | 2022 |
| Using power-anomalies to counter evasive micro-architectural attacks in embedded systems S Wei, A Aysu, M Orshansky, A Gerstlauer, M Tiwari 2019 IEEE International Symposium on Hardware Oriented Security and Trust …, 2019 | 34 | 2019 |
| SeqL: Secure scan-locking for IP protection S Potluri, A Aysu, A Kumar 2020 21st International Symposium on Quality Electronic Design (ISQED), 7-13, 2020 | 31 | 2020 |
Patrick SchaumontWorcester Polytechnic InstituteAdresă de e-mail confirmată pe wpi.edu