| Leveraging 3D technology for improved reliability N Madan, R Balasubramonian 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007 | 292 | 2007 |
| CHOP: Adaptive filter-based DRAM caching for CMP server platforms X Jiang, N Madan, L Zhao, M Upton, R Iyer, S Makineni, D Newell, ... HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010 | 199 | 2010 |
| A case for guarded power gating for multi-core processors N Madan, A Buyuktosunoglu, P Bose, M Annavaram 2011 IEEE 17th International Symposium on High Performance Computer …, 2011 | 114 | 2011 |
| Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy N Madan, L Zhao, N Muralimanohar, A Udipi, R Balasubramonian, R Iyer, ... 2009 IEEE 15th International Symposium on High Performance Computer …, 2009 | 95 | 2009 |
| Scalable and reliable communication for hardware transactional memory SH Pugsley, M Awasthi, N Madan, N Muralimanohar, R Balasubramonian Proceedings of the 17th international conference on Parallel architectures …, 2008 | 55 | 2008 |
| CHOP: Integrating DRAM caches for CMP server platforms X Jiang, N Madan, L Zhao, M Upton, R Iyer, S Makineni, D Newell, ... IEEE micro 31 (1), 99-108, 2010 | 45 | 2010 |
| Power efficient approaches to redundant multithreading N Madan, R Balasubramonian IEEE Transactions on Parallel and Distributed Systems 18 (8), 1066-1079, 2007 | 36 | 2007 |
| Guarded power gating in a multi-core setting N Madan, A Buyuktosunoglu, P Bose, M Annavaram Computer Architecture: ISCA 2010 International Workshops A4MMC, AMAS-BT …, 2012 | 17 | 2012 |
| A research retrospective on amd's exascale computing journey GH Loh, MJ Schulte, M Ignatowski, V Adhinarayanan, S Aga, D Aguren, ... Proceedings of the 50th Annual International Symposium on Computer …, 2023 | 10 | 2023 |
| Power-efficient, reliable microprocessor architectures: Modeling and design methods P Bose, A Buyuktosunoglu, CY Cher, JA Darringer, MS Gupta, H Hamann, ... Proceedings of the 20th symposium on Great lakes symposium on VLSI, 299-304, 2010 | 8 | 2010 |
| Guarded, multi-metric resource control for safe and efficient microprocessor management P Bose, A Buyuktosunoglu, N Madan US Patent 8,527,994, 2013 | 5 | 2013 |
| Power-efficient approaches to reliability N Madan, R Balasubramonian Technical Report UUCS-05-010, 2005 | 4 | 2005 |
| Asynchronous Microengines for Network Processing N Madan School of Computing, University of Utah, 2006 | 3 | 2006 |
| A first-order analysis of power overheads of redundant multi-threading N Madan, R Balasubramonian Proceedings of the Workshop on the System Effects of Logic Soft Errors (SELSE), 2006 | 3 | 2006 |
| Allocation of resources when processing at memory level through memory request scheduling A Dutu, N Jayasena, Y Eckert, N Madan, S Puthoor US Patent 12,204,774, 2025 | 2 | 2025 |
| Approach for managing near-memory processing commands and non-near-memory processing commands in a memory controller N Madan, J Kalamatianos US Patent 12,066,950, 2024 | 2 | 2024 |
| Scheduling Processing-in-Memory Requests and Memory Requests N Madan, JR Alsop, A Dutu, M Islam, Y Eckert, NS Jayasena US Patent App. 17/954,784, 2024 | 2 | 2024 |
| Reusing remote registers in processing in memory J Kalamatianos, V Agrawal, N Madan US Patent 12,175,073, 2024 | 1 | 2024 |
| Adaptive scheduling of memory and processing-in-memory requests A Dutu, NS Jayasena, N Madan US Patent 12,131,026, 2024 | 1 | 2024 |
| DRAM row management for processing in memory N Madan, Y Eckert, V Agrawal, J Kalamatianos US Patent 12,026,401, 2024 | 1 | 2024 |
